Look-up table structure with embedded carry logic

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S041000

Reexamination Certificate

active

11707187

ABSTRACT:
A look up table (LUT) structure, comprising: a first intermediate LUT stage comprising a LUT value input and an output; and a configurable multiplexer (MUX) comprising: an input coupled to a carry in logic signal; and an output coupled to said LUT value input of first intermediate LUT stage; wherein, said first intermediate LUT stage output generates a carry out logic signal.

REFERENCES:
patent: 4706216 (1987-11-01), Carter
patent: 4870302 (1989-09-01), Freeman
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 6134173 (2000-10-01), Cliff et al.
patent: 6208163 (2001-03-01), Wittig et al.
patent: 6275065 (2001-08-01), Mendel
patent: 6331789 (2001-12-01), Or-Bach
patent: 6353920 (2002-03-01), Wittig et al.
patent: 6448808 (2002-09-01), Young et al.
patent: 6466052 (2002-10-01), Kaviani
patent: 6515511 (2003-02-01), Sugibayashi et al.
patent: 6750674 (2004-06-01), Kundu et al.
patent: 6801052 (2004-10-01), Pugh et al.
patent: 6888373 (2005-05-01), Kaptanoglu et al.
patent: 6915323 (2005-07-01), Chang et al.
patent: 6937064 (2005-08-01), Lewis et al.
patent: 6957245 (2005-10-01), Tam
patent: 6990508 (2006-01-01), Mohammed et al.
patent: 2001/0003428 (2001-06-01), Or-Bach
patent: 2001/0048320 (2001-12-01), Lee et al.
patent: 2002/0186044 (2002-12-01), Agrawal et al.
patent: 2003/0001615 (2003-01-01), Sueyoshi et al.
patent: 2003/0085733 (2003-05-01), Pugh et al.
Seals & Whapshott, “Programmable Logic—PLDs and FPGAs”, 1997, pp. 102-117, McGraw-Hill, USA, no month.
Ashok K. Sharma, “Programmable Logic Handbook—PLDs, CPLDs, & FPGAs”, 1998, pp. 99-171, McGraw-Hill, USA, no month.
E. Ahmed, J. Rose, “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density”, FPGA 2000, Monterey, CA, 2000, no month.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Look-up table structure with embedded carry logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Look-up table structure with embedded carry logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Look-up table structure with embedded carry logic will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3860108

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.