Look-up table based logic macro-cells

Details Look-up table based logic macro-cells Look-up table based logic macro-cells

2007-04-24

2007-04-24

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

11350628

ABSTRACT:
A programmable look up table (LUT) structure that offers higher logic packing capacity over conventional LUT structures for programmable logic devices is disclosed. A programmable LUT structure comprising a first stage and one or more intermediate stages and a last stage, wherein at least one of said intermediate stages or the last stage further comprises: a primary input received in true and compliment logic levels, and an output; and two LUT values, said primary input coupling one of said LUT values to said output, wherein at least one of said LUT values further comprises: a secondary input and a configurable data value; and a programmable means to select either the secondary input or the data value as the LUT value.

REFERENCES:
patent: 4706216 (1987-11-01), Carter
patent: 4870302 (1989-09-01), Freeman
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 6134173 (2000-10-01), Cliff et al.
patent: 6208163 (2001-03-01), Wittig et al.
patent: 6275065 (2001-08-01), Mendel
patent: 6331789 (2001-12-01), Or-Bach
patent: 6351152 (2002-02-01), Reddy et al.
patent: 6448808 (2002-09-01), Young et al.
patent: 6515511 (2003-02-01), Sugibayashi et al.
patent: 6801052 (2004-10-01), Pugh et al.
patent: 7075332 (2006-07-01), Young et al.
patent: 2001/0003428 (2001-06-01), Or-Bach
patent: 2001/0048320 (2001-12-01), Lee et al.
patent: 2002/0186044 (2002-12-01), Agrawal et al.
patent: 2003/0001615 (2003-01-01), Sueyoshi et al.
patent: 2003/0085733 (2003-05-01), Pugh et al.
patent: 2004/0155676 (2004-08-01), Kaptanoglu et al.
Seals & Whapshott, “Programmable Logic—PLDs and FPGAs”, 1997, pp. 102-117, McGraw-Hill, USA, no month.
Ashok K. Sharma, “Programmable Logic Handbook—PLDs, CPLDs, & FPGAs”, 1998, pp. 99-171, McGraw-Hill, USA, no month.
E. Ahmed, J. Rose, “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density”, FPGA 2000, Monterey, CA, 2000, no month.

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