Long line receiver for CMOS integrated circuits

Details Long line receiver for CMOS integrated circuits Long line receiver for CMOS integrated circuits

2000-10-25

2003-02-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06526552

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to repeater circuits in very large scale integration (VLSI) circuits, and in particular to a replacement for repeaters which reduces signal transition delay on long lines.
In today's high frequency VLSI chips, delays through both active gates and wires have become equally important in determining the total critical speed path delay. As process technology and supply voltage are scaled, the active gate delay comes down quickly. The gate delay can fall into the sub nano-second range easily with today's advanced processes and scaled supply voltages. On the other hand, wire delay does not scale well due to the increased coupling capacitance and the increased series resistance in finer wires. Inductance also becomes significant with newer processes.
The use of repeaters or buffers in long wires can alleviate this delay problem. The RC time constant of a long wire follows the square rule relationship with its length. Doubling the wire length quadruples the delay time at the end of the wire. On the other hand, the delay is only doubled when compared to the original wire delay (plus any added repeater gate delay) with the insertion of a repeater at the mid-point. This is an improvement in delay time when compared to the case without the use of repeaters.
Repeaters have been used recently in high frequency chip design to resolve the long wire delay problem. The procedure can be described as follows: with an existing routed chip, all long signal wires are analyzed and identified for critical nets. This can be done using a SPICE program to simulate the signal net with the proper lumped RC model. Once repeater placement is identified, they can be inserted in the signal line where they are needed. The repeater cell can reside in a standard cell block, in a data path block, or in a stand-alone repeater block. However, they all occupy extra spaces in the layout.
In a high frequency VLSI chip running above 500 Mhz the required number of repeaters is quite significant. It was estimated that more than 15,000 repeaters are needed for a chip with die size of 18 mm×18 mm, compared to a few hundred for a 200 Mhz or less chip.
The repeaters are essentially dedicated buffers which can be located at different positions on the chip. When a repeater is needed, the wire position where it is needed is broken and routed to the repeater and back. The estimated wire distance between each repeater is about 4 mm for the 500 Mhz chip. Depending on how close the repeater block happens to be, this additional wire routing can add additional delays.
Addition of repeaters is typically a heuristic activity that creates re-working of a circuit layout and a re-evaluation of the impact in a logic negation (since an inverter adds a logic inversion) and timing (since the inverter itself adds its intrinsic delay as well as amplification). Hence a hardware means that could help reconstitute the signal without inversion and without additional delay would help resolve this problem.
FIG. 1A
is a diagram of a typical computer system in which repeaters or other mechanisms may be used. A microprocessor
10
is connected by a bus
11
to a memory
13
. Inside the microprocessor
10
are a number of clusters or logic blocks, such as clusters
12
,
14
,
16
,
18
and
20
. These clusters can be logic blocks, memory arrays, or other group circuitry. In-between the clusters are channels, such as channels
22
,
24
and
26
. The clusters would typically have drivers and receivers along their edges, such as driver/receiver arrays
28
and
30
on cluster
14
and driver/receiver arrays
32
and
34
on cluster
12
. An example of a long line is shown as long line
40
, which goes from a driver in array
30
to a receiver in array
38
. A repeater
42
is placed in the middle of the line to speed the signal transition. As can be seen, the repeaters need to be placed typically after the rest of the circuitry has been laid out, and either need to be placed in the routing channels themselves, or in other locations.
FIG. 1B
is a diagram of long line
40
connected between a driver
44
and a receiver
46
. The driver, shown in simplified form, consists of a PMOS transistor
48
connected between line
40
and a positive voltage supply
50
. An NMOS transistor
52
is connected between line
40
and ground
54
.
Similarly, on the receiver, a PMOS transistor
56
is connected between an output line
58
and positive voltage supply
50
. An NMOS transistor
60
is connected between output line
58
and ground
54
. Please note that a positive voltage supply and ground are used only as examples, and other voltage levels could be used. Shown on the far left is an input signal A, and on the far right an output signal {double overscore (A)}, indicating two inversions through the driver and receiver.
FIG. 1C
illustrates the circuit of
FIG. 1B
with a repeater
42
added. The repeater includes a similar arrangement of a PMOS transistor
62
and an NMOS transistor
64
. As illustrated by the signal and output line
58
, the three bars over the A show that the signal has been inverted again, such that this output is the inverse of the input signal A.
FIG. 2
shows an alternate approach. Instead of a repeater which inverts, a keeper
66
is used. The keeper is a regenerative cross-coupled weak amplifier. The keeper will hold the wire's voltage at its initial setting until the wire's voltage reaches a trigger level, at which point the keeper creates positive feedback, taking the wire voltage to its compliance value, either VDD or GND.
SUMMARY OF THE INVENTION
The present invention provides a clamping circuit which is connected to each long line, preferably adjacent the receiver. The clamping circuit biases the long line at the trigger threshold of the receiver. Thus, instead of amplifying the signal as a repeater will do, the present invention clamps the line to the threshold, thus allowing a faster response since the line doesn't have to be charged or discharged from a lower or higher level to the threshold. This thus speeds up the transition at the receiver without requiring a repeater or a keeper.
The clamping circuit of the invention also reduces the node impedance at the receiver input, thus making the wire less susceptible to coupled interference from other signals.
In one embodiment, the clamping circuit is a feedback circuit. The node voltage can be sensed and converted into two currents fed back into the long line. The feedback circuit can take a variety of forms, and can be connected from the receiver output to its input, or from an intermediate point in the receiver to its input. In one embodiment, the feedback circuit is between two legs of a current mirror that forms a part of the receiver.
The present invention improves the noise margin while preserving the low impedance attributes of the long fine, thus giving more immunity to interference. Speed is enhanced because the voltage excursions are limited and the receiving end has low impedance.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5124578 (1992-06-01), Worley et al.
patent: 5465255 (1995-11-01), Tanaka et al.
patent: 5488705 (1996-01-01), LaBarbera
patent: 5818782 (1998-10-01), Kotani et al.
patent: 5994919 (1999-11-01), Jain
patent: 6038188 (2000-03-01), Akamatsu
patent: 6184717 (2001-02-01), Crick
patent: 6275088 (2001-08-01), Jain
patent: 6351171 (2002-02-01), Balhiser

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