Logical verification apparatus and method for memory control...

Details Logical verification apparatus and method for memory control... Logical verification apparatus and method for memory control...

2005-07-19

2005-07-19

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06920593

ABSTRACT:
A CPU model issues a memory access request to a memory control circuit by executing a verification test program. A transaction monitor monitors a transaction generated on a system bus, and detects and holds a transaction of memory access from the CPU model. A memory model responds to access from the memory control circuit, and acquires transaction information of that access. A memory access checker logically verifies the memory control circuit using the transaction information acquired by the memory model, and the transaction information held by the transaction monitor.

REFERENCES:
patent: 6501690 (2002-12-01), Satoh

Affiliated with

Also associated with

Rating

Logical verification apparatus and method for memory control... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logical verification apparatus and method for memory control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logical verification apparatus and method for memory control... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3431557