Electronic digital logic circuitry – Threshold
Reexamination Certificate
1997-10-10
2002-05-07
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Threshold
C326S039000, C326S045000
Reexamination Certificate
active
06384624
ABSTRACT:
BACKGROUND OF THE INVENTION
Description of Related Art
The neuron MOS transistor (hereinbelow shortened to neuMOS) is a multi-input MOS transistor having a plurality of input gates, which calculates the weighting addition of all input signals and controls the ON OFF state of the transistor; such transistors have been the subject of a considerable amount of research in recent years as devices having a variety of functions.
It is possible to think of the neuMOS as dealing with multivalued signals within the device; it is capable of globally realizing a binary logical circuit using multivalues locally. When a logical circuit is designed using neuMOS, it is possible to greatly reduce the number of transistors in comparison with CMOS.
In the neuMOS, the MOSFET gate is made floating, and the structure is such that a plurality of input gate electrodes are coupled via a capacity with the floating gate. When a neuMOS logical circuit is actually constructed, a neuMOS inverter format having a CMOS structure is employed. The structure of the neuMOS inverter, and a circuit diagram thereof, are shown in FIG.
8
.
If the coupling capacity of one input gate of a neuMOS inverter is fixed at Cc, then when the circuit inputs are connected to a number a of input gates, then it is possible to view the coupling capacity of the circuit inputs as a C
c
. Now, if the input voltage in the circuit input I
i
is represented by V
i
, the coupling capacity of I
i
is represented by ciCc (where c
i
is an integer), and the parasitic capacity of the neuMOS inverter is represented by C
0
, then the potential &phgr; of the floating gate is represented by the following:
[
Arithmetic
Formula
1
]
φ
=
∑
i
=
1
n
c
i
C
c
V
i
C
TOT
(
1
)
C
TOT
=
C
0
+
G
·
C
c
G
=
∑
i
=
1
n
c
i
(
2
)
In the above formula, G represents the total number of input gates of the neuMOS inverter.
The output voltage of the neuMOS inverter changes based on the size relationship between the floating gate potential &phgr; and the inversion threshold voltage Vth of the neuMOS inverter. The voltage V
OUT
of the output OUT of the neuMOS inverter can be expressed as the formula hereinbelow using formula (1).
[
Arithmetic
Formula
2
]
V
OUT
=
{
V
DD
(
∑
i
=
1
n
c
i
C
c
V
i
C
TOT
<
V
th
)
V
SS
(
∑
i
=
1
n
c
i
C
c
V
i
C
TOT
>
V
th
)
(
3
)
If Vth is set to &ggr;V
DD
/2[V] (&ggr;=G·C
c
/C
TOT
), and a variable V
i
corresponding to 1 when V
i
is V
DD
[V], and to 0 when V
i
is C
SS
[V] is introduced, then it is possible to view the neuMOS inverter as an element which realizes the following threshold function from formula (3).
[
Arithmetic
Formula
3
]
f
(
x
)
=
{
1
(
∑
i
=
1
n
c
i
x
i
<
G
2
)
0
(
∑
i
=
1
n
c
i
x
i
>
G
2
)
x
=
(
x
1
,
⋯
,
x
n
)
(
i
=
1
,
⋯
,
n
)
,
x
i
∈
{
0
,
1
}
(
4
)
Changing the way in which the neuMOS inverter is viewed, by causing the values (mC
c
/C
TOT
) V
DD
[V] (m=0, . . . , G) which may be taken by the floating gate potential &phgr; to correspond to logical values m, the neuMOSinverter may be thought of as dealing with multivalued signals in a voltage mode within the device. In this way, G represents the total number of input gates of the neuMOS inverter, and simultaneously represents the number of multivalued levels which may be handled within the device.
Since an increase in G is linked to an increase in the multivalued levels handled in the device, it becomes possible to realize a variety of logical functions using one element, and it is possible to design logical circuits having even fewer elements. However, on the other hand, since C
TOT
is proportional to G, from formula (2), the value of the size C
c
/C
TOT
) V
DD
of the change in potential which must be discriminated on the floating gate becomes even smaller. The minimum value of the change in potential which is to be discriminated on the floating gate is determined by the inversion threshold voltage V
th
of the inverter, the size of the variation in the coupling capacity of the inputs, and the like. That is to say, the upper limit of G is determined by the precision of the device manufacturing process. The upper limit of G has an effect on the reliability of the circuit operation, so that this serves as an extremely strong constraint on the design of the neuMOS circuit.
As described above, the neuMOS inverter can be regarded as a threshold element which realizes formula (4). However, since the threshold function can not express a freely selected logical function, in order to realize a freely selected logical function using neuMOS, it is necessary to adopt a circuit structure in which a plurality of neuMOS inverters are combined.
A neuMOS circuit fulfilling the conditions stated below can be considered as one neuMOS circuit structure which realizes freely selected logical functions.
1. The circuit comprises a number n of circuit inputs and a number N from &ngr;
1
to &ngr;
N
of neuMOS inverters, and the value of G of all the neuMOS inverters is constant.
2. All circuit inputs, V
DD
, and GND are inputted into all neuMOS inverters within the circuit. Furthermore, the coupling capacities with respect to the circuit input I
i
are constant in all neuMOS inverters.
3. In addition to all circuit inputs, V
DD
, and GND, the outputs of the neuMOS inverters &ngr;
2
, . . . , &ngr;
N
are applied to neuMOS &ngr;
1
as inputs.
In the above circuit, signals are outputted from the circuit inputs through a maximum of 2 neuMOS inverters, so that this circuit will hereinafter be termed a 2-stage neuMOS circuit. The network structure of a 4-element 2-stage neuMOS circuit, in which the neuMOS inverters &ngr;
1
, &ngr;
2
, &ngr;
3
, and &ngr;
4
are indicated by circles is shown in FIG.
9
. In
FIG. 9
, a standard CMOS inverter is provided in order to amplify the output &ngr;
1
.
The capacitive coupling of each neuMOS inverter is determined as given below.
c
i
C
c
: the capacitive coupling with respect to the input I
i
of each neuMOS inverter.
c
k
D
C
c
: the capacitive coupling with respect to the V
DD
input of &ngr;
k
.
c
k
S
C
c
: the capacitive coupling with respect to the V
SS
of &ngr;
k
.
&agr;
j
C
c
: the capacitive coupling with respect to the &ngr;
j
output of &ngr;
1
.
At this time, the value of G of each neuMOS inverter is given by the formula below.
[
Arithmetic
Formula
4
]
G
=
∑
i
=
1
n
c
i
+
c
D
1
+
c
S
1
+
∑
j
=
2
n
α
j
(
v
1
)
=
∑
i
=
1
n
c
i
+
c
D
i
+
c
S
i
(
v
2
,
…
,
v
N
)
Here, if it is assumed that c
2
D
> . . . >c
N
D
, then applying formula (4), the 2-stage neuMOS circuit realizes the following function.
[
Arithmetic
Formula
5
]
f
(
x
)
=
{
{
0
(
∑
i
=
1
n
c
i
x
i
<
G
2
-
c
D
1
-
∑
j
=
2
N
α
j
)
1
(
∑
i
=
1
n
c
i
x
i
>
G
2
-
c
D
1
-
∑
j
=
2
N
α
j
)
(
∑
i
=
1
n
c
i
x
i
<
G
2
-
c
D
2
)
{
0
(
∑
i
=
1
n
c
i
x
i
<
G
2
-
c
D
1
-
∑
j
=
k
N
α
j
)
1
(
∑
i
=
1
n
c
i
x
i
>
G
2
-
c
D
1
-
∑
j
=
k
N
α
j
)
(
G
2
-
c
D
k
-
1
<
∑
i
=
1
n
c
i
x
i
<
G
2
-
c
D
k
)
(
k
=
3
,
…
,
N
)
{
0
(
∑
i
=
1
n
c
i
x
i
<
G
2
-
c
D
1
)
1
(
∑
i
=
1
n
c
i
x
i
>
G
2
-
c
D
1
)
(
G
2
-
c
D
N
<
∑
i
=
1
n
c
i
x
i
)
(
5
)
Formula (5) expresses a multiple threshold function having a plurality of threshold values, in which the output changes each time the value of the weighting addition exceeds a threshold value. If the multiple threshold function does not constrain the number
Ike Kenjiro
Yasuura Hiroto
Auduong Gene N.
Knuth Randall J.
Nelms David
Yasuura Hiroto
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