Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-28
2006-11-28
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07143375
ABSTRACT:
The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section7performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB5records the results of the structural matching as an identifier for each element. A subcone extracting section8extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section9performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section10displays only those subcones for which the logical equivalence verification has resulted in mismatch.
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Kumon Yuki
Maruyama Terunobu
Nakamura Takeo
Satou Mitsuru
Takagi Miki
Dimyan Magid Y.
Fujitsu Limited
Staas & Halsey , LLP
Thompson A. M.
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