Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Bipolar transistor
Reexamination Certificate
2000-12-07
2002-06-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Bipolar transistor
C326S040000, C326S046000, C326S105000, C365S219000, C365S220000, C365S221000
Reexamination Certificate
active
06411128
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logical circuit for serializing and outputting a plurality of signal bits simultaneously read from a memory cell array or the like, and in particular, a logical circuit with the timing margin of control signals required for the operation control expanded.
2. Description of the Related Art
There is a method for simultaneously specifying a plurality of addresses of a memory cell on the basis of one input address. There is a memory specification, called burst length, in which an address to be selected next is determined on the basis of an input address, and the above-described specifying method is enabled by the burst length. From data stored in a plurality of addresses simultaneously specified, data bits are burst-output in serial. In addition, by the CAS latency standard, the time period front an address input to a start of data bit output to the outside is specified.
FIG. 1
is a block diagram showing the configuration of a conventional logical circuit. This conventional logical circuit is a circuit to which 4-bit signals (burst length: 4) simultaneously addressed from a memory cell array are input in parallel and from which they are burst-output in serial.
As shown in
FIG. 1
, four input bit lines BL
1
through BL
4
connected to the memory cell array are provided to the conventional logical circuit. Latch circuits L
1
and L
5
are connected to the input bit line BL
1
, latch circuits L
2
and L
6
are connected to the input bit line BL
2
, latch circuits L
3
and L
7
are connected to the input bit line BL
3
, and latch circuits L
4
and L
8
are connected to the input bit line BL
4
. A first latch circuit group is composed of the latch circuits L
1
through L
4
and a second latch circuit group is composed of the latch circuits L
5
through L
8
.
Switches SW
1
and SW
5
are respectively provided between the input ends of the latch circuits L
1
and L
5
and their common connection point. Switches SW
1
and SW
5
are controlled by control signals t
1
and t
2
, respectively. Switches SW
3
and SW
7
are respectively provided between the input ends of the latch circuits L
3
and L
7
and their common connection point. Switches SW
3
and SW
7
are controlled by the control signals t
1
and t
2
, respectively
Switches SW
2
and SW
6
are provided respectively between the input ends of the latch circuits L
2
and L
6
and their common connection point. Switches SW
2
and SW
6
are controlled by the control signals t
1
and t
2
, respectively. In addition, Switches SW
4
and SW
8
are respectively provided between the input ends of the latch circuits L
4
and L
8
and their common connection point. Switches SW
4
and SW
8
are controlled by the control signals t
1
and t
2
, respectively.
The output ends of the latch circuits L
1
through L
8
are connected in common to a node N
1
, and switches SW
11
through SW
18
are respectively connected between the node N
1
and output ends of the latch circuits L
1
through L
8
. The switches SW
11
through SW
18
are controlled by control signals t
A
through t
H
, respectively.
In addition, there is provided an output circuit
101
to which the node N
1
is connected. In the output circuit
101
, a switch SW
21
one end of which is connected to the node N
1
is provided. The switch SW
21
is controlled by a control signal t
Z
. The other end of the switch SW
21
is connected to the output terminal OUT.
Explanation will be given of operation of the conventional logical circuit configured as described above.
FIG. 2
is a timing chart that shows the operation of the conventional logical circuit.
The conventional logical circuit operates in synchronism with an external clock CLK. One cycle of the external clock CLK is, for example, 10 nsec. The CAS latency (CL) is 2, in which, after 2 clocks from input of the address in the memory cell array, data bit stored in the address is output.
When 4-bit data are read out simultaneously from the memory, the 4-bit data are propagated in parallel to input bit lines BL
1
through BL
4
. These data bits are denoted by D
1
, D
2
, D
3
, and D
4
. Also data bits successively read out thereafter are denoted by D
5
, D
6
, D
7
, D
8
, . . . D
n
. Then, the control signal t
1
rises and the switches SW
1
through SW
4
are turned on. As a result, to the latch circuits L
1
through L
4
, which composes the first latch circuit group, the data bits D
1
through D
4
are latched, respectively.
Thereafter, the control signals t
2
and t
1
rise alternately every 1 clock and the data bits D
5
through D
8
are latched to the latch circuits L
5
through L
8
, which composes the second latch circuit group, respectively, and the data bits D
9
through D
12
are latched to the latch circuits L
1
through L
4
, respectively, and the data read out from the memory cell array are alternately latched to the latch circuit groups alternately by 4 bits.
In the meantime, on the output side of the latch circuits L
1
through L
8
, the control signals t
A
, t
B
, t
C
, t
D
, t
E
, t
F
, t
G
and t
H
rise successively every ¼ clock of the external clock CLK. The control signal t
Z
becomes active in synchronism with rising of all the control signals t
A
through t
H
. It should be noted that the control signal t
A
becomes active more than 1 clock faster than the data bits D
9
is latched. If the control signal t
A
becomes active in timing slower than that timing, data will be destroyed because at least the data bits D
4
is not output in timing when the data bits D
9
through D
12
are latched.
In this way, 4-bit data simultaneously read out from the memory cell array are serialized and output.
However, since in the above-mentioned conventional logical circuit, the control signal t
Z
becomes active in synchronism with rising of all the control signals t
A
through t
H
, the length of one cycle of the control signal t
Z
is ¼ times as much as the length of one cycle of the external clock CLK, as shown in FIG.
2
. If the length of one cycle of the external clock CLK is 10 nsec., the length of one cycle of the control signal t
Z
is 2.5 nsec., which is extremely short. If the duty ratio is 50%, the activation and deactivation controls must be carried out every 1.25 nsec. Consequently) the timing margin is extremely narrow, causing a problem of difficult control. With respect to the control signals t
A
through t
H
, it is not as much as the control signal t
Z
, but activation and deactivation controls must be carried out every 2.5 nsec., and the timing margin is also narrow.
As described above, in order to simultaneously read out, serialize, and output a plurality of data bits, at least the same number of latch circuits to latching the data as the number of the data bits simultaneously read out is required. When the output of data bit is delayed by the CAS latency standard or a long data retention period is unable to be set, a data bit already latched is destroyed it a next new data bits arrives from the memory cell array before all the data are output from the latch circuits. To prevent this, the number of latch circuits may be increased, but since the longer the burst length or the higher the operation speed, the more increased is the number of simultaneous readouts from the memory cell array, and consequently, the increase of latch circuits as a result of this will become extremely larger and it is not desirable from the viewpoint of space saving, reduced cost and the like. Consequently, all the latched data must be output before new data arrives from the memory cell array by the use of the control signal t
Z
, which operates at a high speed. However, as described above, there is a problem, in that timing margin of the control signal t
Z
is extremely narrow and it is difficult to control its activation and deactivation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a logical circuit that can secure wide timing margin for control signals even under the high-speed operation and that can imp
Hayes & Soloway P.C.
NEC Corporation
Tan Vibol
Tokar Michael
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