Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-07-17
2001-04-17
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S404000, C257S391000, C257S345000, C326S036000, C326S058000
Reexamination Certificate
active
06218713
ABSTRACT:
This application is based on Japanese Patent Application No. 9-28128 filed on Feb. 12, 1997, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to semiconductor logical circuits, flip-flop circuits and storage circuits particularly of a multivalued logic type.
b) Description of the Related Art
Most of conventional semiconductor logical circuits, flip-flop circuits and storage circuits adopt a binary logic. For example, one memory cell of a static RAM of a binary logic type is constituted of six MOS transistors. A storage density of a memory can be increased by reducing an area of a semiconductor substrate occupied by one memory cell.
There is a limit, however, in reducing a memory cell area. It is effective for increasing a storage capacity without reducing a memory cell area to adopt a multivalued logic type.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide semiconductor logical circuits, flip-flop circuits and storage circuits of a multivalued logic type.
It is another object of the present invention to provide a storage circuit device capable of increasing a storage capacity without reducing one memory cell area.
According to one aspect of the present invention, there is provided a logical circuit device comprising a MOS transistor having a source region, a drain region, a channel region defined between the source region and the drain region, and a gate electrode formed above the channel region, respectively formed on a semiconductor substrate, wherein the amplitude of a voltage applied to the gate electrode necessary for making the channel region conductive is not level throughout the channel region in the width direction.
As the voltage applied to the gate electrode is gradually increased, current first flows through a partial region conductive at that voltage of the channel region. As the voltage applied to the gate electrode is further increased, the width of the partial region where current flows is broadened. Since current flows also through the new conductive portion, the increase factor of current becomes large. The input/output characteristics of the MOS transistor take therefore a gently sloped step shape or wave form. A logical circuit of a multilevel logic type can be formed by using a gentle slope portion of the input/output characteristics for each state of multivalued logic levels.
According to another aspect of the present invention, there is provided a flip-flop circuit device comprising: first and second inverter circuits each formed by a three-terminal semiconductor circuit device having one control terminal and two current terminals, current flowing through the two current terminals being controlled by an electric signal applied to the control terminal, and two graphs intersecting at least 5 points or more when the two graphs are superposed, one graph representing the input/output characteristics of the first inverter circuit and the other graph representing an inverse function of the input/output characteristics of the second inverter circuit; and first and second interconnections for inputting output signals from the first and second inverter circuits to the second and first inverter circuits respectively.
According to another aspect of the present invention, there is provided a storage circuit device comprising: first and second inverter circuits each formed by a three-terminal semiconductor circuit device having one control terminal and two current terminals, current flowing through the two current terminals being controlled by an electric signal applied to the control terminal, and two graphs intersecting at least 5 points or more when the two graphs are superposed, one graph representing the input/output characteristics of the first inverter circuit and the other graph representing an inverse function of the input/output characteristics of the second inverter circuit; first and second interconnections for inputting output signals from the first and second inverter circuits to the second and first inverter circuits respectively; a bit line to be applied with an electric signal corresponding to information to be stored; a switching element connected between the second interconnection and the bit line, a conductive state and a non-conductive state of the switching element being selected by an externally applied select signal; and a word line for supplying the select signal to the switching element.
If there are five cross points between the graph representing the input/output characteristics of the first inverter circuit and the graph representing the inverse function of the input/output characteristics of the second inverter circuit, three cross points among the five cross points can be used as stable states. A storage circuit of a three-valued logic type can be obtained by using each stable state for each of multivalued levels.
As described above, a semiconductor logical circuit of a multivalued logic type can be realized by forming two or more regions having different threshold values in the channel region of a MOS transistor. A storage circuit of a multivalued logic type can be realized by a combination of inverter circuits of a multivalued logic type. The storage density can be increased by using a storage circuit of a multivalued logic type.
REFERENCES:
patent: 5017817 (1991-05-01), Yanakawa
patent: 5576573 (1996-11-01), Su et al.
patent: 5587668 (1996-12-01), Shibata
patent: 5635749 (1997-06-01), Hong
patent: 5786618 (1998-07-01), Wen
patent: 3-218070 (1991-09-01), None
Kemerer, IBM TDB vol. 14 No. 4 9/71 “Storage cell . . . Transistors” pp. 1077-1078.
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Jackson, Jr. Jerome
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