Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-13
2004-01-13
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06678870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the technology of optimizing a logical circuit, and more specifically to the technology of optimizing the delay of a signal traveling in the logical circuit at the initial stage of designing the logical circuit.
2. Description of the Related Art
Conventionally, a number of suggestions of optimizing the delay of a critical path extracted from a logical circuit have been made as the technology of allowing a computer to optimize the delay which occurs in a logical circuit, that is, to optimize the delay of a signal traveling in the logical circuit, for example, Japanese Patent Publication No.5-151310, Japanese Patent Publication No.11-120222.
Since an enormous number of processes are required to extract a critical path by the above mentioned conventional technology, it is necessary to operate a high-performance computer for a long time.
In the conventional delay optimizing process performed by a computer, the optimizing process is performed only on fanouts on the critical path. That is, the relationship among a plurality of driven blocks configuring the fanouts has not been considered. Therefore, the driving ability (needed for a driven block with a view to driving the driven block) of the driven blocks in the critical path becomes too large, thereby possibly causing the installation circuit area of the driven blocks to be enlarged too much to reserve the driving ability.
Furthermore, in the conventional process, the external input/output terminal of a logical circuit to be designed, which is connected to another circuit, has been optimized by assuming that a common buffer device is connected to the external input/output terminal of other circuit. Additionally, the driving ability is fixed to a predetermined value for an input pin connected to the external input/output terminal in the logical circuit. To change the driving ability, the circuit containing the input pin has to be replaced with another circuit.
Furthermore, in the conventional process, the load capacity of a network (wiring connecting circuit blocks) does not reflect the information obtained by the installation design after performing a delay optimizing process. That is, it is not considered in an optimizing process, or an approximate value is used. Therefore, a circuit delay may not be successfully improved after the installation design although the circuit delay of a logical circuit is optimized.
Additionally, in the conventional process, it is necessary to issue an instruction for each device or a path to set a block not to be optimized at a user request not to perform a delay optimizing process, etc.
Furthermore, when a delay optimizing process is performed in the conventional process, a target circuit is automatically converted and output. Therefore, the logical circuits before and after the process have to be compared with each other to know the contents of the replacement of the devices by the optimization.
SUMMARY OF THE INVENTION
The present invention has been developed to solve the above mentioned problems, and aims at providing a new method for optimizing a circuit delay in a logical circuit.
The present invention works on the premises that an optimizing process is performed by a system or a method on a delay of a signal traveling in a logical circuit configured by connecting a plurality of circuit blocks by changing the specification about a primitive device specified for each circuit block for use in configuring the circuit blocks into the specification about another primitive device having the same function and a different driving ability value.
The logical circuit delay optimization system is an aspect of the present invention, and includes: a driving ability value computation unit for computing a driving ability value required for a target circuit block based on the delay rate of the circuit block indicating the rate of the delay of a signal traveling in the circuit block by the load capacity value provided for the circuit block, the driving ability value of a prior stage circuit block determined by the device specified for the prior stage circuit block connected at a stage prior to a target circuit block for which the specification is changed, and the load capacity value provided for the target circuit block by connecting another circuit block at a stage subsequent to the target circuit block; and a change unit for changing the specification of the device used in the target circuit block based on the driving ability value obtained in the computation.
According to the above mentioned aspect of the present invention, the optimum device to be used in a target circuit block can be selected based on the characteristic value of the circuit block connected at a stage prior to or subsequent to the target circuit block. As a result, the delay optimization can be realized for the logical circuit without extracting a critical path by selecting the optimum devices for all circuit blocks, thereby reducing the number of processes required for the delay optimization.
Another aspect of the logical circuit delay optimization system according to the present invention includes: a slack value computation unit for computing a slack value of a circuit block; a driving ability value distribution unit for distributing to each subsequent stage circuit block a driving ability value for each subsequent stage circuit block before changing the specification determined by a device specified as the subsequent stage circuit block when an output of a circuit block in a logical circuit is connected to one of a plurality of subsequent stage circuit blocks which are provided at the subsequent stages of the circuit block based on differences among the slack values computed for the subsequent stage circuit blocks with a sum of the driving ability values of the subsequent stage circuit blocks maintained; a subsequent stage circuit block driving ability value computation unit for computing a driving ability value required for the subsequent stage circuit block by assuming that the driving ability value distributed by the driving ability value distribution unit as a driving ability value of a circuit block provided at a stage prior to the subsequent stage circuit block; and a subsequent stage circuit block change unit for changing the specification of a device for use in the subsequent stage circuit block based on the driving ability value obtained in the computation.
According to the above mentioned aspect of the present invention, a larger driving ability value is assigned to a subsequent stage circuit block having a shorter timing value and a smaller driving ability value is assigned to a subsequent stage circuit block having a longer timing value according to the slack value of each circuit block, and the optimizing process can be performed with a signal path having a longer signal delay prioritized, thereby realizing delay optimization indicating well balanced driving abilities.
A further aspect of the logical circuit delay optimization system according to the present invention includes: a slack value computation unit for computing a slack value of a circuit block; a driving ability ratio computation unit for computing the ratio of the sum of the driving ability values of subsequent stage circuit blocks before changing the specification determined by a device specified for the subsequent stage circuit block to a driving ability value of a circuit block having a smaller timing value according to a slack value in the subsequent stage circuit blocks before changing the specification when an output of a circuit block in a logical circuit is connected to one of a plurality of subsequent stage circuit blocks which are provided at the subsequent stages of the circuit block; a driving ability value computation unit for computing a driving ability value required for the subsequent stage circuit block indicated as having the smallest timing value according to a slack value based on the rate of the driving ability value computed by the driving ability ratio c
Furukawa Eiji
Mizuno Rimi
Okada Yumi
Dimyan Magid Y.
Siek Vuthe
Staas & Halsey , LLP
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