Logical circuit capable of uniformizing output delays for differ

Details Logical circuit capable of uniformizing output delays for differ Logical circuit capable of uniformizing output delays for differ

1997-07-01

1999-11-16

Lam, Tuan T.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

326121, 326119, H03K 190948

Patent

active

059864788

ABSTRACT:
An N-input transistor logic circuit includes two or four series-connected transistor arrays connected between two power lines. The gates of the transistors are connected to the N inputs to account for varying parasitic input capacitances, and equalizes the resulting time delays between the N-inputs and the logical unit output. Specifically, in each of the arrays each of the transistors is connected to one of the N inputs, and is separated from a first power line by X other transistors in the respective array. For each of the input terminals, the sum of X for all the arrays is a constant, namely, 2N-2 for four arrays and N-1 for two arrays.

REFERENCES:
patent: 3986041 (1976-10-01), Buckley, III et al.
patent: 4716308 (1987-12-01), Matsuo et al.
patent: 5391941 (1995-02-01), Landry
patent: 5479112 (1995-12-01), Choi et al.

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