Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2001-11-13
2003-01-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S083000
Reexamination Certificate
active
06509761
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logical circuit used for constituting an LSI, and particularly belongs to a circuit design technique for improving the operating speed of the logical circuit and for reducing power consumption, so as to accelerate a two-wire logical circuit using two signal lines to express a logical value.
2. Description of the Related Art
A logical gate is used as a constituent element for a digital LSI manufactured by CMOS process. As shown in
FIG. 1
, a standard CMOS logical gate is constituted such that a PMOS network
97
consisting of PMOS transistors are arranged between a VDD power source line
27
and an output
96
and that an NMOS network
98
comprising NMOS transistors
98
are arranged between a GND power source line
28
and the output
96
. Either the PMOS network
97
or the NMOS network
98
becomes conductive in accordance with the value of an input
95
and outputs either a VDD potential or a GND potential to the output
96
. As the concrete circuit configuration of the CMOS logical gate stated above, a NOT gate (inverter) is shown in
FIG. 2 and a
NAND gate is shown in
FIG. 3. A
conventional standard CMOS logical gate has been designed so that delay time generated since the level of the signal value of an output
96
rises from an L (low)-level, i.e., the GND potential to an H (high)-level, i.e., the VDD potential becomes equal to delay time generated when the level of the signal value of the output
96
falls from the H-level to the L-level as much as possible in delay time generated since the input
95
changes until the output
96
changes. Here, the delay time normally indicates time required since the voltage of the input signal changes to exceed a certain threshold value until the voltage of the output signal changes to exceed the same threshold value. In many cases, the threshold voltage of the input of the NOT gate is used as this threshold value.
The delay time generated from the change of the input to the change of the output is specified as the sum of an internal delay and a load delay. In case of the logical gate referred to as inverted logic, as is represented by the NOT gate and the NAND gate, in which the signal polarity of the input is inverted from that of the output, the load delay to be described later almost determines the delay time of the logical gate. The load delay is determined by the current driving capabilities of the PMOS network
97
and the NMOS network
98
and the magnitude of a capacitance acting as a load. As the current driving capabilities are higher, the delay time of the logical gate becomes shorter. The delay time generated when the output signal rises is almost inversely proportional to the current driving capability of the PMOS network
97
. In the NOT gate shown in
FIG. 2
, the delay time thereof is determined by the current driving capability of the NMOS transistor which is only one transistor included in the NMOS network
98
. The current driving capability of each of PMOS and NMOS transistors is proportional to the gate width w of the transistor. However, it is known that the driving capability of the PMOS transistor is about half the driving capability of the NMOS transistor which has the same gate width w because of the difference in carrier mobility. Accordingly, to make the delay time generated when the output signal rises equal to that generated when the output signal falls, it is necessary to set the gate width w of the PMOS transistor to be twice as large as the gate width w of the NMOS transistor in the NOT gate. If such a gate width ratio is set, however, the area of the logical gate becomes too large when the layout thereof is designed. Practically, therefore, the gate width w of the PMOS transistor is set to be about 1.5 times as large as the gate width w of the NMOS transistor in the NOT gate.
FIG. 2
shows that the PMOS has a width of 2.1 micrometers and the NMOS has a width of 1.4 micrometers. As stated above, the gate width ratio of the PMOS to the NMOS is “1.5”. In this case, the current driving capability of the PMOS transistor is, quite naturally, only 0.75 times as high as the current driving capability of the NMOS transistor. As a result, the delay time generated when the output signal rises is longer than the delay time generated when the output signal falls. On the other hand, the input threshold voltage of the NOT gate is decreased and the substantial increase of delay time is rather small, so that the above-stated ratio is practically used.
In the NAND gate shown in
FIG. 3
, unlike the NOT gate, the PMOS transistor and the NMOS transistor have an equal gate width w of 2.1 micrometers. In the case of the NAND gate shown therein, since two NMOS transistors are connected in series, the current driving capability of the NMOS network
98
is lower than that of a network including one transistor. The gate width w of the NMOS transistor is, therefore, set large so as to compensate for the decreased current driving capability. The current driving capability of a network becomes lower as the number of transistors connected in series increases. This requires the gate width w of the transistor to be set large. However, if two transistors are connected in series, the current driving capability of the network does not become half due to the non-linearity of operation characteristics. It is. estimated herein that the current driving capability of the network having two serially connected transistors becomes ⅔ as high as that of the network including one transistor, and the gate width w of each transistor of the former network is set ⅔ times as large as that of the transistor of the latter network. By doing so, the ratio of the current driving capability of the PMOS network
97
to that of the NMOS network
98
of
FIG. 3
becomes equal to the ratio in the NOT gate shown in FIG.
2
. As can be seen, in the CMOS logical gate according to the conventional technique, the current driving capability of the PMOS network
97
and that of the NMOS network
98
are adjusted to have setting values, respectively, by adjusting the gate width w of a transistor. Here, if it is assumed that the CMOS logical gate is designed so that the current driving capability of the PMOS network
97
is considerably asymmetric with that of the NMOS network
98
, delay time generated when the output rises and delay time generated when the output falls becomes considerably asymmetric with each other, as well. If so, the longer delay time generally determines the upper limit of the operating speed of the circuit. Due to this, the CMOS process has been conventionally designed so that output rise delay time and output fall delay time are balanced as much as possible.
Another conventional technique will be described. Among logical circuits used as the constituent elements of a digital LSI manufactured by the CMOS process, there is a DCVS-DOMINO circuit which has one of the circuit constitutions enabling the highest operating speed. Publication “Kan M. Chu, et. al., A Comparison of CMOS circuit Techniques: Differential Cascade Voltage Switch Logic Versus Conventional Logic. IEEE Journal of Solid-State Critics, Vol. SC-22, No. 4, Aug. 1987 pp. 528-532” shows the comparison result of the performance of the DCVS-DOMINO circuit configuration with that of the other circuit configuration and highlights that the DCVS-DOMINO circuit ensures high speed.
FIG. 4
shows the circuit configuration of the DCVS-DOMINO. The DCVS-DOMINO circuit is classified as a circuit having a configuration referred to as two-wire dynamic logic. The DCVS-DOMINO circuit operates while the operation state thereof is switched between two types of states referred to as a precharge state and an evaluate state. If a precharge input
92
shown in
FIG. 4
is at an L-level, the DCVS-DOMINO circuit is in a precharge state. In this state, two PMOS transistors
87
become conductive, an NMOS transistor
88
is cut off, the inputs
85
and
86
of output inverters
83
and
84
are at an
A-I-L Corporation
Cho James H.
Ladas & Parry
Tokar Michael
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