Logic verification method for semiconductor device

Details Logic verification method for semiconductor device Logic verification method for semiconductor device

2005-04-26

2005-04-26

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S016000

Reexamination Certificate

active

06886144

ABSTRACT:
In designing a semiconductor device, a method of verifying an upper-hierarchy logic including a lower-hierarchy logic. First, a first verification logic having an output terminal, which is equivalent to an input terminal of the lower-hierarchy logic, and an input terminal, which is equivalent to an output terminal of the lower-hierarchy logic. Then, a second verification logic including only the input terminal and output terminal of the lower-hierarchy logic is produced, and an operational verification of the upper-hierarchy logic is executed using the first and second verification logics. This method eliminates the need for performing an operational verification of the lower-hierarchy logic at the time of the operational verification of the upper-hierarchy logic.

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Chen et al., “Model aggregation for hierarchical control synthesis of discrete event systems”, Proceedings of the 39th IEEE Conference on Decision and Control, vol. 1, pp. 418-423, Dec. 12, 2000.

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