Logic transformation and gate placement to avoid routing...

Details Logic transformation and gate placement to avoid routing... Logic transformation and gate placement to avoid routing...

2011-08-23

2011-08-23

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S101000, C716S104000, C716S105000

Reexamination Certificate

active

08006210

ABSTRACT:
A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

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USPTO Office Action (Mail Date Mar. 7, 2011) for U.S. Appl. No. 12/015,631, filed Jan. 17, 2008.

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