Logic timing diagram display apparatus

Details Logic timing diagram display apparatus Logic timing diagram display apparatus

1983-03-23

1985-11-19

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340721, 340744, G06F 314

Patent

active

045545367

ABSTRACT:
Apparatus for displaying a logic timing diagram on a raster scan type display device is disclosed. A logic signal is sampled and representations thereof stored in a RAM. The RAM contents are read repeatedly in synchronism with a raster scan operation, and the read-out signal is delayed by a predetermined time which is shorter than one bit cycle of the read-out signal. Logical gating functions, OR, exclusive-OR and NAND gates, receive the delayed and undelayed signals, and provide output signals from which the display of the "High" level, edges and "Low" level of the logic timing diagram are derived. Since it is not necessary to convert the logic signal to display codes and rewrite a display RAM, high speed scrolling and magnification can be obtained quickly and easily.

REFERENCES:
patent: 3968499 (1976-07-01), Lowe et al.
patent: 4364036 (1982-12-01), Shimizu
patent: 4425643 (1984-01-01), Chapman et al.

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