Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2011-04-12
2011-04-12
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S104000, C327S200000, C716S030000
Reexamination Certificate
active
07924057
ABSTRACT:
DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA -blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed.
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Tiri Kris J. V.
Verbauwhede Ingrid
Cho James H.
Knobbe Martens Olson & Bear LLP
Tabler Matthew C
The Regents of the University of California
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