Logic stages with inversion timing control

Details Logic stages with inversion timing control Logic stages with inversion timing control

2011-02-01

2011-02-01

Cho, James (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S098000, C327S392000

Reexamination Certificate

active

07880504

ABSTRACT:
A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversion-timing control unit that controls inversion timing for the voltage level inverted by the voltage-level inverting unit.

REFERENCES:
patent: 6320421 (2001-11-01), Akita et al.
patent: 6583655 (2003-06-01), Takahashi et al.
patent: 6646474 (2003-11-01), Forbes
patent: 2006-211494 (2006-08-01), None
Rakesh Vattikonda, et al., “Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design”, Design Automation Conference, 43rdACM/IEEE, 2006, pp. 1047-1052.

Affiliated with

Also associated with

Rating

Logic stages with inversion timing control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic stages with inversion timing control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic stages with inversion timing control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2644256