Logic signal validity verification apparatus

Details Logic signal validity verification apparatus Logic signal validity verification apparatus

1995-06-01

1996-06-18

Hudspeth, David R.

Electronic digital logic circuitry

Reliability

326 21, 326 52, 371 572, H03K 1921

Patent

active

055281656

ABSTRACT:
A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.

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Boudeile, "One Out of N Detector", IBM Tech. Disc. Bull., vol. 13, No. 6, Nov. 1970, pp. 1490-1491.

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