Logic processing apparatus, semiconductor device and logic...

Details Logic processing apparatus, semiconductor device and logic... Logic processing apparatus, semiconductor device and logic...

2006-12-05

2006-12-05

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S098000, C327S201000, C327S203000

Reexamination Certificate

active

07145365

ABSTRACT:
Off-leak electric current is reduced in the operation mode where a circuit is actually operating.In the state in which the power supply voltage is constantly applied to the front stage flip-flops11to13and rear stage flip-flops21to23,for example, data held in the flip-flops11to13at rising of the clock signal CK is processed in a logic gate circuit network31to which the supply voltage is applied during a low level period of the clock signal CK, and then, the processed data is held in the flip-flops21to23.In the case where the power supply time to the logic gate circuit network31is set to minimum, off-leak electric current of the logic gate circuit network31can be reduced.

REFERENCES:
patent: 5646555 (1997-07-01), Morinaka
patent: 6452421 (2002-09-01), Saito
patent: 6459302 (2002-10-01), Nakaizumi
patent: 6788109 (2004-09-01), Kitagawa
patent: 6788110 (2004-09-01), Endo

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