Logic module including versatile adder for FPGA

Details Logic module including versatile adder for FPGA Logic module including versatile adder for FPGA

2010-06-25

2011-12-27

Ismail, Shawki S (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C708S235000

Reexamination Certificate

active

08085064

ABSTRACT:
A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.

REFERENCES:
patent: 3728532 (1973-04-01), Pryor
patent: 5349250 (1994-09-01), New
patent: 5481206 (1996-01-01), New et al.
patent: 5724276 (1998-03-01), Rose et al.
patent: 5818255 (1998-10-01), New et al.
patent: 5898319 (1999-04-01), New
patent: 6108191 (2000-08-01), Bruchhaus et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6154053 (2000-11-01), New
patent: 6157209 (2000-12-01), McGettigan
patent: 6288570 (2001-09-01), New
patent: 6708191 (2004-03-01), Chapman et al.
patent: 6836147 (2004-12-01), Nakaya
patent: 6873181 (2005-03-01), Pedersen
patent: 7016932 (2006-03-01), Kantabutra et al.
patent: 7129748 (2006-10-01), McCollum et al.
patent: 7185035 (2007-02-01), Lewis et al.
patent: 7218139 (2007-05-01), Young et al.
patent: 7663400 (2010-02-01), Plants
patent: 7770879 (2010-08-01), Kazama et al.
patent: 7772879 (2010-08-01), Feng et al.
patent: 2003/0001613 (2003-01-01), Nakaya
patent: 2009/0243652 (2009-10-01), Dorairaj et al.
patent: 2010/0100864 (2010-04-01), Plants
Office Action mailed Jul. 19, 2010 in co-pending U.S. Appl. No. 12/645,863, filed Dec. 23, 2009, entitled Flexible Carry Scheme for Field Programmable Gate Arrays.
Actel Axcelerator Family FPGAs, Detailed Specifications (v2.6) http://www.actel.com/documents/AXDetailedSpecs—DS.pdf, pp. 2-43 through 2-46, Mountain View, CA, USA.
Altera Cyclone III Device Handbook, vol. 1: http://www.altera.com/literature/hb/cyc3/cyc3—ciii51002.pdf, pp. 2-1, 2-2, 2-4, 2-5 & 2-6, San Jose, CA, USA.
Cyclone Architecture, Cyclone Device Handbook, vol. 1, CSXXXXXX, [Internet] http://www.altera.com/literature/hb/cyc/cyc—c51002.pdf, Altera Corp., x pages, Jan. 2007, San Jose, CA, USA. (Figs. 2-7, pp. 2-10).
Cyclone II Architecture, Cyclone Device Handbook, vol. 1, CSII51002-3.1, [Internet] http://www.altera.com/literature/hb/cyc2/cyc2—cii51002.pdf, Altera Corp., x pages, Feb. 2007, San Jose, CA, USA. (Fig. 2-4, p. 2-6).
Altera Stratix III Device Handbook, vol. 1: http://www.altera.com/literature/hb/stx3/stx3—siii51002.pdf, pp. 2-1, 2-13 to 2-19, San Jose, CA, USA.
Logic Elements and Logic Array Blocks in Cyclone III Devices, CS XXXXXXX, [Internet] http://www.altera.com/literature/hb/cyc3/cyc3—ciii51002.pdf, Altera Corp, X pages, Jul. 2007, San Jose, CA, USA (Fig. 2-5, p. 2-5).
Stratix Architecture, S510023.2, [Internet] http://www.altera.com/literature/hb/stx/ch—2—vol—1.pdf, Altera Corp., Jul. 2005, x pages, San Jose, CA, USA. (Fig. 2-7, p. 2-11).
Stratix II Architecture, S5xxxxxxx, [Internet] http://www.altera.com/literature/hb/stx2/stx2—sii51002.pdf,, Altera Corp, May 2007, x pages, San Jose, CA, USA. (Figs. 2-11, 2-12, 2-13, 2-14, pp. 2-14 to 2-19).
Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices, http://www.altera.com/literature/hb/stx3/stx3—siii51002.pdf, x pages, San Jose, CA, USA. (Figs. 2-11, 2-12, 2-13, 2-14, pp. 2-14 to 2-19).
“Lattice LatticeSC/M Family Data Sheet, DS1004 Version 01.8, Lattice Semiconductor Corp., http://www.latticesemi.com/documents/DS1004.pdf, Nov. 2007, pp. 2-1, 2-3 to 2-6, Hillsboro, OR, USA.”
Xilinx Virtex-5 User Guide, UG190 (v3.1) Sep. 11, 2007, http://www.xilinx.com/support/documentation/user—guides/ug190.pdf, pp. Cover, 168-170, San Jose, CA, USA.
Virtex 2.5 V Field Programmable Gates Arrays, Xilinx Data Book 1999, Xilinx® Corporation, Feb. 16, 1999 (Version 1.3), pp. 3-8 & 3-9, San Jose, CA, USA.
Spartan and SpartanXL Families Field Programmable Gate Arrays, Xilinx Data Book 1999, Xilinx® Corporation, Jan. 6, 1999 (Verison 1.4), pp. 4-18, 4-19, & 4-20, San Jose, CA, USA.
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays, DS025-2 (V2.2), Module 2 of 4, [Internet] http://www.xilinx.com/support/documentation/data—sheets/ds025-2.pdf, Xilinx, Inc., Sep. 10, 2002, X pages, San Jose, CA, USA. (Fig. 5, p. 4).
Virtex-II Platform FPGAs: Complete Data Sheet, DS031 (v3.5), Module 2 of 4, [Internet] http://www.xilinx.com/support/documentation/data—sheets/ds031.pdf, Xilinx, Inc., Nov. 5, 2007, X pages, San Jose, CA, USA. (Fig. 16, p. 13).
Virtex-4 FPGA User Guide, UG070 (v2.4), [Internet] http://www.xilinx.com/support/documentation/user—guides/ug070.pdf, Xilinx, Inc., Apr. 10, 2008, X pages, San Jose, CA, USA. (Fig. 5-2, p. 185).
Virtex-5 FPGA User Guide, UG190 (v4.1), [Internet] http://www.xilinx.com/support/documentation/user—guides/ug190.pdf, Xilinx, Inc., Apr. 25, 2008, x pages, San Jose, CA, USA. (Fig. 5-3, p. 173).
Filo, David et al., “Technology Mapping for a Two-Output RAM-Based Field Programmable Gate Array”, European Design Automation Conf. (EDAC) 1991, p. 534-538, IEEE Computer Society Press, Los Alamitos, CA, USA.
Ling, H., High Speed Binary Adder, IBM J. Res. Develop., [Internet] www.cs.ucsd.edu/classes/fa06/cse246/lingadder.pdf, May 1981.
Cormen, Thomas H. et al., “Introduction to Algorithms,” The MIT Press, 1990, pp. 662-663.

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