Logic-merged memory

Details Logic-merged memory Logic-merged memory

2000-08-03

2003-11-18

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000

Reexamination Certificate

active

06649984

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices and more specifically to a semiconductor integrated circuit device having a logic circuit and a dynamic random access memory (DRAW merged on the same chip.
2. Description of the Background Art
In order to achieve high level processing at a high speed, semiconductor integrated circuit devices called “system LSI” or “logic-merged memory” having a memory and a logic circuit integrated on the same chip have been implemented.
FIG. 26
is a schematic diagram showing the general configuration of a conventional semiconductor integrated circuit device. In
FIG. 26
, semiconductor integrated circuit device
1
includes a logic circuit
2
to perform a prescribed processing and a DRAM (Dynamic Random Access Memory) circuit
3
which stores data to be used by logic circuit
2
.
DRAM circuit
3
includes memory cell arrays MA
0
to MA
3
each having a plurality of DRAM memory cells arranged in a matrix of rows and columns and DRAM peripheral circuitry DPH placed in a cross-shaped central region among these memory cell arrays MA
0
to MA
3
. DRAM peripheral circuitry DPH includes circuits to perform accessing operation to memory cell arrays MA
0
to MA
3
and data transfer between logic circuit
2
and DRAM circuit
3
and an internal voltage generating circuit to generate internal voltage.
In semiconductor integrated circuit device
1
, data transfer between logic circuit
2
and DRAM circuit
3
is performed through internal interconnection lines on a chip on which semiconductor integrated circuit device
1
is formed. An internal data bus is no subject to limitation by the number of pin terminals, and therefore a large bit width is allowed for the internal data bus, so that the number of data bits which can be transferred at a time can be increased and high speed data transfer is implemented.
The data bus is formed of an internal interconnection line, and a control signal line between logic circuit
2
and DRAM circuit
3
is also an internal interconnection line. Such an internal interconnection line has a line capacitance smaller than the wires on a printed circuit board, can transfer data/signal at a high speed and can be driven with small current driving capability due to the small line capacitance, so that the current consumption can be significantly reduced. In such a semiconductor integrated circuit device having a DRAM circuit and a logic circuit merged, both the requirements for the reliability of the DRAM circuit and the high speed performance of the logic circuit must be satisfied.
FIG. 27A
is a schematic cross sectional view of a MOS transistor which is a component of logic circuit
2
shown in FIG.
26
. In
FIG. 27A
, the MOS transistor which is a component of logic circuit
2
(hereinafter referred to as “logic transistor LTR”) includes high concentration impurity regions
2
b
and
2
c
formed on a surface of a semiconductor substrate region
2
a
, and a gate electrode layer
2
d
formed on a channel region between these impurity regions
2
b
and
2
c
with a gate insulating film
2
e
underlaid. Gate insulating film
2
e
has a film thickness, Toxl. Logic circuit
2
must operate at a high speed with low current consumption. To this end, the thickness Toxl of gate insulating film
2
e
of logic transistor LTR is made sufficiently small, and the absolute value Vth of the threshold voltage of the logic transistor is made sufficiently small. By making the absolute value of the threshold voltage small, logic transistor LTR is allowed to be set to a sufficiently deep on state even under a low power supply voltage condition, and the internal node (signal line) can be charged/discharged with large current driving capability.
FIG. 27B
is a schematic cross sectional view of a MOS transistor (insulated gate field effect transistor) included in DRAM circuit
3
. The MOS transistor which is a component of the DRAM circuit shown in
FIG. 27B
(hereinafter referred to as “DRAM transistor DTR”) includes high concentration impurity regions
3
b
and
3
c
formed spaced apart on a surface of a semiconductor substrate region
3
a
and a gate electrode layer
3
d
formed on a channel region between impurity regions
3
b
and
3
c
, with a gate insulating film
3
e
underlaid. Gate insulating film
3
e
has a thickness Toxm.
The thickness Toxm of gate insulating film
3
e
of DRAM transistor DTR is made larger than the thickness Toxl of gate insulating film
2
e
in logic transistor LTR. In DRAM circuit
3
, a selected word line is provided with a boosted voltage Vpp higher than the power supply voltage, and a bit line isolation gate to selectively connect a bit line and a sense amplifier circuit in a shared sense amplifier arrangement is similarly provided with a high voltage in order to reduce the threshold voltage loss. In order to maintain the reliability even if such high voltages are applied, the thickness Toxm of gate insulating film
3
e
in DRAM transistor DTR is made larger than that of logic transistor LTR.
In conventional semiconductor integrated circuit devices of this kind, Dual Oxide process has been employed, according to which such a DRAM transistor having a thick gate insulating film and a logic transistor having a thin gate insulating film are formed separately on the same chip. In this Dual Oxide process, after gate insulating films for a DRAM transistor and a logic transistor are formed in the same step, the DRAM transistor is masked using resist, and the gate insulating film of the logic transistor is made thin. Then, the gate insulating films for the DRAM transistor and logic transistor are once again made thick. In order to reduce damages of the logic transistor caused at the time of etching and improve the controllability of the thickness of the gate insulating films, the gate insulating film of the logic transistor is once made thin by etching and then thick by for example CVD.
In the DRAM circuit, MOS transistors included in DRAM peripheral circuitry DPH and memory cell arrays MA
0
to MA
3
are all DRAM transistors.
The logic transistor has a small absolute value for the threshold voltage, and therefore has large leakage current in an off state (off leakage current). In order to use the logic transistor in a DRAM circuit having a significantly large number of elements, leakage current in the DRAM circuit in a stand-by state is not negligible, which makes difficult the use of the logic transistor in the DRAM circuit.
In the DRAM transistor, the thickness Toxm of gate insulating film
3
e
is made larger and the absolute value of the threshold voltage is set higher. Meanwhile, a sense amplifier circuit to sense, amplify and latch memory cell data on bit lines as will be described is required to perform the sensing operation with high sensitivity and at a high speed, and the absolute value of the threshold voltage of the MOS transistor must be made small. Such different threshold voltages are implemented by adjusting the threshold voltage by ion-implantation into the channel regions.
If transistors required to have a small absolute value for the threshold voltage such as MOS transistors in sense amplifier circuits included in memory cell arrays MA
0
to MA
3
are formed by DRAM transistors as described above, the number of manufacturing steps and the number of masks increase for the purpose of adjusting the threshold voltages by ion-implantation to lower the threshold voltages, which pushes up the cost of the semiconductor integrated circuit device.
In addition, the DRAM peripheral circuitry includes MOS transistors of a relatively high threshold voltage and cannot operate as fast as the logic circuit.
However, if a logic transistor having a low threshold voltage (small absolute value for the threshold voltage) is used for a low threshold voltage MOS transistor in the DRAM circuit for the purpose of simplifying the manufacturing process, the following problems are encountered.
In the DRAM circuit, acceleration test to screen d

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