Logic gates for reducing power consumption of gallium arsenide i

Details Logic gates for reducing power consumption of gallium arsenide i Logic gates for reducing power consumption of gallium arsenide i

1995-11-13

2000-06-20

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 31, H03K 190952

Patent

active

060781947

ABSTRACT:
A method and apparatus for reducing power consumption by gallium arsenide integrated circuits divides the integrated circuit into higher and lower frequency sections. The high frequency sections require a substantial portion of the system clock period to resolve their longest combinatorial paths. The lower frequency sections require a relatively small portion of the system clock period to resolve their longest combinatorial logic paths. The combinatorial logic paths of each of such lower frequency sections are designed using logic gates which are capable of being decoupled from the chip power supply by way of a power enable input. Edge triggered memory circuits such as flip-flops are also designed using the reduced power logic gates, except for their cross-coupled outputs so that they may retain their state. A dual-output one-shot multivibrator is used to generate the power enable signal used to couple and decouple the logic gates of each lower frequency section from the chip power supply, as well as the clock pulse with which to clock the flip-flops of the lower frequency section. The one-shot generates these control signals based on the positive edge of the system clock. The lower frequency sections thus dissipate virtually no power except during that portion of the system clock period necessary to resolve their longest combinatorial paths.

REFERENCES:
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patent: 4567385 (1986-01-01), Falater et al.
patent: 4763021 (1988-08-01), Stickel
patent: 5294928 (1994-03-01), Cooper et al.

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