Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-07
2005-06-07
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06904573
ABSTRACT:
Techniques are disclosed for estimating the signal propagation delays within a circuit, based on a description of the circuit written in a hardware description language (HDL), such as a register transfer language (RTL). Assignment statements in the description which describe the performance of a logical function are modeled using logic gates which perform the function described. A particular function may be modeled using one or more logic gates depending on the number of inputs to the function. The delay associated with performance of the function is estimated by estimating the delay through the circuit used to model the function. Estimates for multiple functions may be combined to estimate the total delay associated with a particular signal path through a circuit.
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Dimyan Magid Y.
Hewlett--Packard Development Company, L.P.
Whitmore Stacy A.
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