Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2000-05-01
2001-07-10
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S095000, C708S702000, C713S324000
Reexamination Certificate
active
06259275
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to the following U.S. Patent applications:
Reference
No.
Title
Inventor
Date
09/158,947
Adder and Multiplier
Beiu
Filed
(‘947
Circuits Employing
September 21,
application)
Logic Gates Having
1998
Discrete, Weighted
Inputs and Methods of
Performing
Combinatorial
Operations Therewith
09/392,811
Conductance-based
Beiu
Filed Sept. 9,
(‘811
Logic Gate and Methods
1999
application)
of Operation and
Manufacturing Thereof
09/406,367
Noise Tolerant
Beiu
Filed Sept.
(‘367
Conductance-based
28, 1999
application)
Logic Gate and Methods
of Operation and
Manufacturing Thereof
09/407,598
Adder Having Reduced
Beiu
Filed Sept.
(‘598
Number of Internal
28, 1999
application)
Layers and Method of
Operation Thereof
The above-listed applications are commonly assigned with the present invention and are incorporated herein by reference as if reproduced herein in their entirety.
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to logic gates and, more specifically, to a logic gate having reduced power dissipation and method of operation thereof.
BACKGROUND OF THE INVENTION
Digital systems are used extensively in computation and data processing, controls, communications and measurement. Digital systems use digital signals that may only assume discrete values. Typically, digital systems use binary signals that employ only two values. Since such systems only use two distinct values, errors caused by component variations are minimized. As a result, a digital system may be designed such that, for a given input, an output thereof is exactly correct and repeatable. This gives rise to the extreme accuracy for which digital systems are well known.
Analog systems, on the other hand, use analog signals that vary continuously over a specified range. Analog systems are thus particularly vulnerable to error, depending on the accuracy of the components used therein. Since digital systems are generally capable of greater accuracy and reliability than analog systems, many tasks formerly performed by analog systems are now performed exclusively by digital systems.
One basic building block of digital systems is a logic gate. Conventional logic gates have one output and one or more inputs. The number of inputs is called the “fan-in” of the gate. The state of the output is completely determined by the state(s) of the input(s). Conventional logic gates are typically created by coupling a number of transistors together to perform a Boolean function (e.g., AND, OR, NOT). The logic gates are then coupled together to form a multi-layer circuit that is capable of performing logical functions (e.g., arithmetic functions).
Increasing processing power is a continuing goal in the development of processors such as microprocessors or digital signal processors (DSPs). Processor designers are generally familiar with three ways to increase the processing power of a central processing unit (CPU). The CPU's clock frequency may be increased so that the CPU can perform a greater number of operations in a given time period. Processors are designed to operate at increasingly high clock frequencies. While a higher clock frequency generally results in increased processing power, the higher clock frequency also increases power dissipation, resulting in higher device operating temperatures. Processor designers, therefore, must address these additional problems to avoid catastrophic device failures.
Another way to increase processing power is to increase input and output data bus width, thereby allowing the CPU to process a greater amount of code and data. Early processors were packaged using dual in-line packaging (DIP) technology. Increasing the width of the data buses was both expensive and unrealistic, often resulting in extremely large device packages. Today, with the use of pin grid array (PGA) packaging, increasing the size of the data buses no longer poses a packaging problem. Of course, a larger number of transistors is required to process the additional information conveyed by the wider data buses, which translates into increased power dissipation by the processor.
Yet another way to increase processing power is to change the internal architecture of the processor to overlap the execution of instructions by, for example, superscaling. This method also requires the addition of a large number of transistors, since entire processing stages or execution units must be duplicated. Performing a large number of instructions in parallel may also result in data dependency problems. Further, the additional transistors also increase power dissipation.
With the rise of portable and personal computing, power dissipation has become an important factor in the design of processors. Processors employed in desktop or server-based applications may be designed to maximize speed with little regard for power consumption. Processors employed in laptop, palmtop or other portable devices, however, must be designed with power consumption in mind due to the often limited capabilities of the batteries powering the portable devices. Since the processor includes a large number of logic gates, reducing power dissipation in the individual logic gates can accordingly reduce the power consumption of the processor as a whole.
Accordingly, what is needed in the art is a logic gate operable at high frequency that overcomes the disadvantages of prior art logic gates.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides, for use with a logic gate having a logic circuit that dissipates DC power during an operation thereof, a circuit for, and method of, decreasing the DC power dissipated in the logic circuit. The present invention further provides a logic gate and a processor (such as a microprocessor or a digital signal processor) incorporating the circuit or the method. The logic gate has at least two binary inputs adapted to receive corresponding input binary digits. In one embodiment, the circuit includes: (1) a combinatorial logic power down circuit that develops a power down signal as a function of an input-data signal and at least one of the input binary digits and (2) a switch, coupled to the power down circuit, that interrupts DC current to at least a portion of the logic circuit as a function of the power down signal.
In an alternative embodiment, circuit includes: (1) a combinatorial logic power down circuit that develops a power down signal as a function of an input-data signal and an output binary digit generated at an output of the logic gate and (2) a switch, 20 coupled to the power down circuit, that interrupts DC current to at least a portion of the logic circuit as a function of the power down signal.
The present invention therefore introduces the broad concept of employing a combinatorial logic power down circuit that implements a Boolean function to develop a power down signal that causes at least a portion of the logic gate to turn off to reduce power dissipation. This reduces the power consumption of the logic gate as a whole without materially affecting its speed performance.
In one embodiment of the present application, the logic gate is a conductance-based logic gate as described in the '811 application. Of course, the principles of the present invention are applicable to a wide variety of logic gates.
In one embodiment of the present invention, the power down circuit includes at least one pass transistor. The use of the pass transistor may significantly simplify an implementation of the combinatorial logic power down circuit. Further, the pass transistor implementation of the combinatorial logic power down circuit may consume less power than other conventional implementations.
In one embodiment of the present invention, the power down circuit develops the power down signal as a function of all of the input binary digits. In an alternative embodiment, the power down circuit develops the power down signal as a function of only some of the input binary digits. In either case, the powe
Chang Daniel D.
RN2R, L.L.C.
Tokar Michael
LandOfFree
Logic gate having reduced power dissipation and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic gate having reduced power dissipation and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic gate having reduced power dissipation and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2500119