Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-19
2003-05-13
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S023000
Reexamination Certificate
active
06564367
ABSTRACT:
BACKGROUND OF THE INVENTION
In general, the present invention relates to a logic dividing method for assigning logic circuits to a module with a plurality of programmable large-scale integrated circuits (LSIs) mounted thereon and relates to a module wiring technology in a logic emulation system for verifying performance and operations of the large-scale integrated circuits. More particularly, the present invention relates to an effective technology applicable to a logic dividing and module wiring system which takes a positional relation with an external interface of a module and operation timings into consideration.
In development of a large-scale integrated circuit which is referred to hereafter as an LSI, it is important that as many defects as possible are detected before a prototype is built. This is because, if a defect is detected after a prototype is built, it will take time to determine a cause of the defect. In addition, since the prototype must be rebuilt if a defect is detected, it is feared that the cost and the development time will increase.
As a solution to the problem, there is logic emulation using a field programmable gate array (which is referred to hereafter as an FPGA) for a programmable large-scale integration circuit. In the logic emulation, a logic circuit to be verified is programmed by using an FPGA and logic of the circuit is verified by actually operating the FPGA in conjunction with an actual product sold in the market or an existing LSI.
In addition, with logic of a logic circuit to be processed becoming large in scale in recent years, the logic circuit is divided into a plurality of FPGAs each serving as a target of circuit implementation. Then, the FPGAs are assembled for carrying out logic emulation.
As logic emulation apparatus for carrying out such logic emulation, there is a technology disclosed in Japanese Patent Laid-open No. Hei 6-3414. According to this technology, logic emulation is carried out by using a module which is called a pseudo LSI and comprises a plurality of FPGAs, a non-volatile memory for storing data of a logic circuit to be verified, a transfer unit for transferring data between the FPGAs and the non-volatile memory and a power supply. As a method to implement such a module, a plurality of FPGAs are mounted on the module as bare chips. Such a module is referred to as a multi-chip module.
In addition, as a typical technique for carrying out logic emulation whereby a logic circuit is divided, being targeted at a plurality of FPGAs and the FPGAs are assembled, a technology is disclosed in a document such as Japanese Patent Laid-open No. Hei 10-312309. As a technique for dividing a logic circuit into a plurality of portions, a technology is disclosed in Japanese Patent Laid-open No. Hei 8-212249.
By referring to a flowchart shown in
FIG. 25
, the following description briefly explains work and processing to generate logic data for logic emulation which uses a logic emulation apparatus disclosed in Japanese Patent Laid-open No. Hei 6-3414, and adopts the logic-emulation technique disclosed in Japanese Patent Laid-open No. Hei 10-312309 as well as the logic-circuit dividing technique disclosed in Japanese Patent Laid-open No. Hei 8-212249.
As shown in
FIG. 25
, the flowchart begins with a step S
2501
at which a logic circuit subjected to logic emulation is input. Then, at the next step S
2502
, the logic circuit input at the step S
2501
is divided, being targeted at a plurality of FPGAs. That is to say, results of the division are each assigned to one of the FPGAs. Then, at the next step S
2503
, the FPGAs are wired on a module for programming the logic circuit input at S
2501
. In actuality, since wiring on the module has been done, pins of each of the FPGAs are associated with logic signals. Then, at the next step S
2504
, in accordance with results of assignment of portions resulting from the division of the logic circuit at the step S
2502
to the FPGAs and pin positions determined at the step S
2503
, placement and wiring of the FPGAs are carried out to create logic data. Finally, at the step S
2505
, logic emulation is carried out by programming the logic data created at the step S
2504
on the FPGAs on the module.
As one of problems encountered in such logic emulation, in a module where the LSI under development and the logic circuit are programmed to operate, the package size, the connection structure and the pin layout vary. Thus, there is raised a problem of a need to individually create both a board for mounting an LSI to be developed and a board for mounting the module described above.
It takes time to create a board for mounting the module described above. In addition, the logic circuit which is programmed on the module and serves as an object of logic verification needs to be connected to another LSI to be actually operated in conjunction with the logic circuit. Thus, the board is created concurrently with the work to design and to divide the logic circuit in many cases. For these reasons, at a point of time the logic circuit is divided, external interface signals of the logic may have been assigned to pins of each connector on the module or assigned to connectors at a connector level even if not assigned to pins of each of the connectors.
In the conventional technology described above, however, the design of a board is not taken into consideration when the logic circuit is divided. Thus, a variety of problems are raised in implementing the logic emulation.
For example, the conventional technology does not consider which connector on the module external interface signals of the logic are to be assigned to when the logic circuit is divided. As a result, there is raised a problem of unavoidable diversion of logic related to external interface signals independent of results of the division and the assignment of the external interface signals to connector pins.
This problem is described in concrete terms as follows. The module described in Japanese Patent Laid-open No. Hei 6-3414 comprises a connector, FPGAs, wires connecting the connector to one or more FPGAs and wires connecting two or more FPGAs.
With an external interface signal assigned to a wire connecting a connector to two or more FPGAs, the external interface signal is propagated to pins of all the FPGAs connected to the connector by the wire. Thus, a pin of any of the FPGAs not logically using the external interface signal becomes unnecessary and other necessary logic signals can not be assigned. If a number of such wires are used, the number of virtually usable pins in each FPGA becomes small. Thus, the number of wires connecting a connector pin to an FPGA on a 1-to-1 basis increases. This holds true of wires connecting an FPGA to another. With a connector pin connected to an FPGA on a 1-to-1 basis, it is desirable to assign logic related to an external interface signal assigned to a connector pin to an FPGA connected to the connector pin if the operating speed of the logic or a wire resource on the module is taken into consideration.
To put it more concretely, assume that external interface signals A and B have been assigned to two pins of a connector directly connected to the same FPGA on the module. In this case, it is desirable to assign logic related to the external interface signals A and B to the FPGA directly connected to the connector as described above.
Since the positions of connector pins are not taken into consideration when logic is divided in accordance with the conventional technology described above, the external interface signals A and B may be assigned to different FPGAs in some cases. In this case, one of the external interface signals A and B is connected directly to logic in another FPGA from a connector by way of an FPGA directly connected to the connector. As a result, there is raised a problem of a reduced operating speed.
In addition, the following problem is also raised. If a logic circuit is divided, a critical-delay path may also be divided into segments assigned to a plurality of FPGAs in some cases. A path is a route of p
Fujii Mototsugu
Morimoto Kazunobu
Tada Osamu
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Niebling John F.
Whitmore Stacy
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