Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-06-07
2002-08-27
Lee, Michael G. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S087000, C326S083000, C326S027000
Reexamination Certificate
active
06441644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic device in which a signal changing with an external load is output within a prescribed range of a through rate such as a rise time or a fall time while suppressing an unnecessary radiation noise.
2. Description of Related Art
A prescribed range is generally standardized for a through rate (for example, a rise time or a fall time) of an output signal of which a level changes with an external load. For example, standards of a Universal Serial Bus (USB) used for computer peripheral apparatuses have been approved. A signal output from a device transmits through the USB at a data rate of 1.5 M bits per second in a low speed data communication. The USB standards relate to a level of the signal output from the device, and the USB standards require that the output signal is accurately raised up and fallen down within a time-period range of from 75 to 300 nanosecond in the low speed data communication on condition that an external load ranges from 200 pF to 600 pF. Therefore, the through rate of the output signal is required to be fixed within a prescribed range.
As a conventional logic device in which a signal is output within a through rate range regulated in the USB standards, an output buffer circuit disclosed in the Published Unexamined Japanese Patent Application No. 17516 of 1999 (H11-17516) has been known.
FIG. 9
is a circuit diagram showing the configuration of the output buffer circuit disclosed in the Patent Application No. 17516 of 1999, and
FIG. 10
is a waveform diagram showing simulation results of level changes of output signals in a low speed operation of the output buffer circuit.
As shown in
FIG. 9
, reference numerals
11
,
12
,
13
,
14
,
15
,
16
,
17
and
18
indicate inverter circuits. Each inverter circuit fundamentally outputs an signal of a high electric level (H level) corresponding to a logical value “1” (positive logic) when a p-channel metal oxide semiconductor (MOS) transistor of the inverter circuit is turned on by receiving a signal of a low electric level (L level) corresponding to a logical value “0” at a gate of the p-channel MOS transistor. Also, each inverter circuit fundamentally outputs an signal of an L level when an n-channel MOS transistor of the inverter circuit is turned on by receiving a signal of an H level at a gate of the n-channel MOS transistor. The Output of each of the inverter circuits
13
,
14
,
15
and
16
is controlled according to enable signals LSB and LS or enable signals FSB and FS. Also, by using a source voltage VDD and a reference voltage VSS (VSS is equal to the ground voltage of 0 V), a threshold voltage (that is, a switching voltage) of each of the inverter circuits
11
,
13
and
14
is a value higher than (VDD−VSS)/2, and a threshold voltage of each of the inverter circuits
12
,
15
and
16
is a value lower than (VDD−VSS)/2. A reference numeral
130
indicates a control circuit, each of reference numerals
140
a
and
140
b
indicates a delay circuit, a reference numeral
151
indicates a first-stage buffer, a reference numeral
152
indicates a second-stage buffer, a reference numeral
153
indicates a third-stage buffer, a reference symbol P
0
indicates a p-channel MOS transistor of the first buffer
151
, and a reference symbol NO indicates an n-channel MOS transistor of the first buffer
151
. A reference symbol P
1
indicates a p-channel MOS transistor of the second buffer
152
, and a reference symbol N
1
indicates an n-channel MOS transistor of the second buffer
152
. A reference symbol P
2
indicates a p-channel MOS transistor of the third buffer
153
, and a reference symbol N
2
indicates an n-channel MOS transistor of the third buffer
153
. A reference symbol Cap indicates a condenser arranged between a node DD and the ground of the voltage VSS.
An operation of the output buffer circuit is described on condition that the logical value of an input signal D is changed from “1” to “0” in a low mode speed operation according to the positive logic. Also, in this low mode operation, the inverter circuits
13
and
15
are controlled by the enable signals LSB and LS to be operable.
When the logical value of an input signal D is changed from “1” to “0”, a level of a signal output from the inverter circuit
17
is heightened as the level of the input signal D becomes lowered, and the signal is input to the inverter circuit
18
. As the level of the signal input to the inverter circuit
18
is heightened, a p-channel MOS transistor PU of the inverter circuit
18
starts to turn off, and an n-channel MOS transistor ND of the inverter circuit
18
starts to turn on. As a result, a charge of the node DD set to the level VDD is discharged to the ground through the n-channel MOS transistor ND. In this case, because the condenser Cap is arranged between the node DD and the ground, as shown in
FIG. 10
, the level of the node DD is gradually changed from the H level (VDD level) to the L level (VSS level).
Because a threshold voltage Vth
11
of the inverter circuit
11
is higher than (VDD−VSS)2, that is, VDD2 in case of VSS=0 V (ground level), as the level of the input signal D is lowered, the level of the input signal D reaches the threshold voltage Vth
11
of the inverter circuit
11
, and the logical value of a signal Pu
1
output from the inverter circuit
11
is changed from “0” to “1” before the level of the input signal D reaches VDD/2.
In contrast, the level of the node DD is gradually lowered while being delayed as compared with the lowering of the level of the input signal D, and the level of the node DD reaches a threshold voltage Vth
13
of the inverter circuit
13
. As a result, as shown in
FIG. 10
, the level of a signal Pu
2
output from the inverter circuit
13
is heightened. That is, the logical value of the signal Pu
2
is changed from “0” to “1”. In this case, the level change of the signal Pu
1
is earlier than that of the signal Pu
2
. Thereafter, the p-channel MOS transistor P
0
of the first-stage buffer
151
and the p-channel MOS transistor P
1
of the second-stage buffer
152
start to turn off. Also, the p-channel MOS transistor P
2
of the third-stage buffer
153
starts to turn off.
Thereafter, when the level of the input signal D continues to be lowered, a p-channel MOS transistor P
10
is rapidly turned on so as to assist the p-channel MOS transistor P
1
of the second-stage buffer
152
to be turned off, and a p-channel MOS transistor P
11
is rapidly turned on so as to assist the p-channel MOS transistor P
2
of the third-stage buffer
153
to be turned off. As a result, as shown in
FIG. 10
, the level of the signal Pu
2
is sharply changed toward the high level (VDD) in the first half of the fall time of the input signal D while changing a waveform of the signal Pu
2
stepwise, and a level of a signal Q of an output pad Q is sharply lowered in the middle of the fall time of the signal Q.
Thereafter, when the level of the input signal D is lowered to a threshold voltage Vth
12
of the inverter circuit
12
lower than VDD/2, the logical value of a signal Pd
1
output from the inverter circuit
12
is changed from “0” to “1”. Therefore, the n-channel MOS transistor NO of the first-stage buffer
151
starts to turn on. However, at this time, the level of the node DD, which is set by discharging the charge of the node DD to the ground through the inverter circuit
18
, is not lowered to a threshold voltage Vth
15
of the inverter circuit
15
. Therefore, the n-channel MOS transistor N
1
of the second buffer
152
and the n-channel MOS transistor N
2
of the third buffer
153
are respectively maintained to an “off” condition.
Thereafter, when the level of the node DD reaches the threshold voltage Vth
15
of the inverter circuit
15
, as shown in
FIG. 10
, the logical value of a signal Pd
2
output from the inverter circuit
15
is changed from “0” to “1”. Therefore, the n-channel MOS transistor N
1
and the n-channel MOS transistor N
2
start to turn o
Burns Doane , Swecker, Mathis LLP
Lee Michael G.
Mitsubishi Denki & Kabushiki Kaisha
Paik Steven S.
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