Logic device

Details Logic device Logic device

1998-04-30

2000-09-19

Tokar, Michael

Electronic digital logic circuitry

Interface

Logic level shifting

326121, 326115, H03K 190185

Patent

active

06121793&

ABSTRACT:
A symmetrical loading and current supply arrangement is described for a differential-type logic means, and symmetrical voltage swings are thereby achieved in the logic output. In a preferred arrangement the output voltages are self-aligned to a CMOS level which facilitate conversion of the differential-type output to CMOS signals.

REFERENCES:
patent: 4728900 (1988-03-01), Nakagawara et al.
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patent: 4806796 (1989-02-01), Bushey et al.
patent: 5148061 (1992-09-01), Hsueh et al.
patent: 5149992 (1992-09-01), Allstot et al.
patent: 5317214 (1994-05-01), Lewis
patent: 5818269 (1998-10-01), Brown et al.
patent: 5877642 (1999-03-01), Takahashi
"Performance of ECL-Compatible 75 Line Driver/Receiver Realised INA 1.2 UM CMOS Technology" Electronics Letters, Sevenhans J. et al. vol. 26, No. 11, May 24, 1990, pp. 764-766.
"ECL-CMOS and CMOS-ECL Interface in 1.2-UM CMOS for 150-MHZ Digital ECL Data Transmission Systems" Steyaert M S J et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1, 1991, pp. 18-23.

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