Logic consolidated semiconductor memory device having memory...

Details Logic consolidated semiconductor memory device having memory... Logic consolidated semiconductor memory device having memory...

1999-12-15

2002-07-30

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189050, C365S225700, C365S230030

Reexamination Certificate

active

06426901

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a logic consolidated semiconductor memory device in which a memory for storing data and a logic circuit for performing a predetermined arithmetic computation of the data are integrated in the same chip.
This application is based on Japanese Patent Application No. 10-358040 filed Dec. 16, 1998, the contents of which is incorporated herein by reference.
FIG. 1
shows a layout of elements on a chip of a conventionally-used logic consolidated semiconductor memory device. As shown in
FIG. 1
, a chip
61
has a logic section
62
, a memory section
63
and an I/O section
64
. The logic section
62
includes a circuit for a predetermined arithmetic computation. The memory section
63
is constituted of a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like.
FIG. 2
is a layout showing an example of a structure of a memory macro cell of a conventionally-used DRAM. To be more specific, this example shows a memory macro cell
71
of the DRAM (2048 rows×16 columns×128 I/O=4M bit). The DRAM memory macro cell
71
has four 1M-bit memory cell array blocks (MCAB)
72
-
1
to
72
-
4
, a data pass block (DPB)
73
, a control block (CTRB)
74
, four memory cell array power supply driver blocks (PWDB)
75
-
1
to
75
-
4
, a power supply generation block (PWGB)
76
,
11
power supply line blocks (PWLB)
77
-
1
to
77
-
11
, and a single power supply line block (PWLB)
78
which are arranged next to each other.
In the bit memory cell array blocks (MCAB)
72
-
1
to
72
-
4
, data line pairs DQ
0
, /DQ
0
to DQ
127
, /DQ
127
are arranged. These data lines pair DQ
0
, /DQ
0
to DQ
127
, /DQ
127
are connected to the data pass block
73
.
The control block
74
contains a buffer holding a row address strobe signal (/RAS), a buffer having a row address, a buffer holding a column addresss strobe signal (/CAS), a buffer holding a column address, and a buffer holding a write enable signal (/WE). The control block
74
not only predecodes the row address and column address but also controls various operations of the memory.
The power source generation block
76
is constituted of a reference voltage generation circuit for generating a reference voltage, such as a band gap reference circuit. Each of the power supply driver blocks
75
-
1
to
75
-
4
generates a substrate potential and a word line driving voltage required for every memory cell array on the basis of the reference voltage generated by the power supply generation block
76
. Each of the power supply line blocks
77
-
1
to
77
-
11
, and
78
has a decoupling capacitor for stabilizing a wiring and a potential of the wiring. The power supply line block
78
differs from the power supply line blocks
77
-
1
to
77
-
11
in wiring pattern and capacitance of the decoupling capacitor. Particularly, the capacitance of the decoupling capacitor of the power supply line block
78
is set larger than those of the power supply line blocks
77
-
1
to
77
-
11
. In some cases, an equalizing circuit for the data line pair is provided in the power supply line block
78
and an equalizing circuit for a column selection line (CSL) is provided in the power supply line blocks
77
-
1
to
77
-
11
.
In a writing mode, an input data passes through the data pass block
73
, a selected data line pair from the pairs DQ
0
, /DQ
0
to DQ
127
, /DQ
127
, and a bit line (not shown) selected from the memory cell array blocks
72
-
1
to
72
-
4
and is supplied to a memory cell. In data-readout mode, a data read out from a selected memory cell is output through the bit line, a selected data line pair from the pairs DQ
0
, /DQ
0
to DQ
127
, /DQ
127
, and the data pass block
73
.
FIG. 3
is a layout showing a detailed structure of the data pass block
73
. The data pass block
73
has a DQ buffer
73
a
connected to the data line pairs DQ
0
, /DQ
0
, DQ
127
, /DQ
127
, a DQ control section
73
b,
a fuse circuit
73
c,
and an input/output (I/O) data buffer
73
d.
The DQ control section
73
b
selects one from the data line pairs DQ
0
, /DQ
0
to DQ
127
, /DQ
127
in accordance with a column address. The fuse circuit
73
c,
which is responsible for replacing a defective column with a normal column, has a fuse box for storing an address of the defective column, a fuse latch circuit, and a fuse control circuit.
When a memory micro cell of a conventional DRAM is formed as shown in
FIG. 2
, it is possible to form a DRAM memory macro cell having a 1×nM bit (n is a natural number) by adding a memory cell array block (MCAB), a power supply driving block (PWDB), a power supply line block (PWLB) and the like. In a conventional technique, although it is possible to increase storage capacity, the number of I/O data lines (data bus) to be connected to the logic section is fixed at
128
. Even if a multiplex function is imparted to the I/O buffer
73
d,
the number of I/O data lines comes to only 64 bits. Furthermore, since the data number is fixed, when the DRAM memory macro cell having a parity bit function is required, an entire DRAM memory macro cell must be newly designed. As a result, longer time is required for designing the DRAM memory macro cell.
BRIEF SUMMARY OF THE INVENTION
The present invention is made in order to overcome the aforementioned problems. An object of the present invention is to provide a semiconductor memory device having a DRAM memory macro cell with an arbitrarily-set number of input/output data lines, and capable of adding a parity bit and a redundancy circuit while preventing an increase of time required for designing.
To attain the aforementioned object, the invention according to a first aspect of the present invention has the following constitution. The semiconductor memory device according to the present invention comprises
a logic circuit arranged on a semiconductor substrate; and
a memory macro arranged on the semiconductor substrate and having a plurality of sub memory macros,
wherein each of the plurality of sub memory macros comprises
a plurality of memory cell arrays;
a data line pair arranged over the plurality of memory cell arrays, for transmitting write data and read-out data;
a holding circuit for holding the write data and the read-out data to be transmitted to the data line pair; and
an input/output data line pair for connecting the holding circuit and the logic circuit.
Furthermore, in the semiconductor memory device, it is desirable that the plurality of memory cell arrays and the holding circuit be arranged in a column direction; the data line pair and the input/output data line pair be extended in the column direction; and the plurality of sub memory macros be arranged in a row direction.
To attain the aforementioned object, the present invention according to a second aspect is constituted as follows. The semiconductor memory device of the present invention comprises:
a logic circuit arranged on a semiconductor substrate; and
a memory macro arranged on the semiconductor substrate and having a plurality of sub memory macros and a redundancy circuit,
wherein each of the plurality of sub memory macros comprises
a plurality of memory cell arrays
a data line pair arranged over the plurality of memory cell arrays, for transmitting write data and read-out data;
a holding circuit for holding the write data and the read-out data to be transmitted to the data line pair;
and
an input/output data line pair for connecting the holding circuit and the logic circuit,
the redundancy circuit comprises
a memory element arranged to each of the sub memory macros, for storing a defective address of a corresponding sub memory macro; and
a control circuit for comparing the defective address of each sub memory macro stored in the memory element with an input address and replacing a defective memory defined by the defective address with a spare memory when the defective address coincides with the input address.
Furthermore, in the semiconductor memory device, it is desirable that the plurality of memory cell arrays and the hold

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