Logic circuits used for address decoding

Details Logic circuits used for address decoding Logic circuits used for address decoding

2001-02-20

2002-07-23

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S093000, C326S095000, C326S112000, C326S119000, C326S121000, C327S333000

Reexamination Certificate

active

06424176

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally logic circuits, and more particularly to logic circuits used for address decoding.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as semiconductor memories, use address decoders to selectively activate a memory cell based on an external address or an internally generated address. During read, write, refresh (DRAM) and erase (EPROM) cycles, decoders can be activated. These decoders will typically be directly in the critical speed path of the device.
An example of a conventional logic circuit, that may be used as a decoder, is set forth in FIG.
13
and is designated by the general reference character
1300
. Conventional logic circuit
1300
contains an input circuit
1310
and a driver circuit
1320
. Input circuit
1310
is a conventional Complementary Metal Oxide Semiconductor (CMOS) 3-input NAND gate containing three n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) (N
12
-N
14
) connected in series between ground (GND) and a logic evaluation node V
13
. The input circuit also contains three p-channel MOSFETS (P
6
-P
8
) connected in parallel between a high power supply (VCC) and logic evaluation node V
13
. The MOSFETS (N
12
-N
14
and P
6
-P
8
) are configured so that each n-channel MOSFET (N
12
-N
14
) and each p-channel MOSFET (P
6
-P
8
) receives a single input (A
13
-C
13
). If all the inputs (A
13
-C
13
) are at a logic high level, then conventional logic circuit
1300
is in a selected state and logic evaluation node V
13
is pulled to GND, which corresponds to a low logic level, through n-channel MOSFETs (N
12
-N
14
). If any of the inputs (A
13
-C
13
) are at a logic low level then at least one of the n-channel MOSFETs (N
12
-N
14
) will be turned off and at least one of the p-channel MOSFETs (P
6
-P
8
) will be turned on. Thus, logic evaluation node V
13
will be pulled to a high logic level VCC, which corresponds to an unselected state.
It is noted that each input is received at the gate of one n-channel MOSFET (N
12
-N
14
) and one p-channel MOSFET (P
6
-P
8
). This causes an input (A
13
-C
13
) to be loaded by a relatively large gate capacitance. Considering that inputs (A
13
-C
13
) are typically addresses and are connected to a large number of such logic circuits
1300
, waveforms of the inputs (A
13
-C
13
) can rise and fall slowly, and/or be rounded at the corners. This can cause reduced circuit operation speeds and also can cause extended time periods of flow through current in which current flows through the input circuit
1310
directly from VCC to GND.
Driver circuit
1320
is connected to receive the logic level at logic evaluation node V
13
and produces a logic output D
13
. Driver circuit
1320
is two inverters (INV
11
and INV
12
) connected in series. The inverters (INV
11
and INV
12
) are CMOS inverters, thus each contain an n-channel MOSFET and p-channel MOSFET. Inverter INV
12
uses relatively large MOSFETs in order to drive a highly capacitive signal line connected to logic output D
13
. Because inverter INV
12
is a CMOS inverter, the logic output D
13
is driven from rail to rail (VDD to GND and vice-versa). This can cause unwanted power consumption due to the charging and discharging of the highly capacitive signal line connected to logic output D
13
.
A p-channel MOSFET will typically source less current than an n-channel MOSFET of the same size due to the lower mobility of the majority carriers or “holes.” Thus, it may take a longer time for logic output D
13
to achieve a trip-point or threshold of the receiving circuit (not shown) when going from logic low to logic high.
Also, the use of a p-channel MOSFET and an n-channel MOSFET in the inverter INV
12
can cause circuit layout inefficiencies because there is a minimum device isolation distance required from an MOSFET and the edge of the well or tank. Because an n-channel and a p-channel MOSFET device is being used, both p-well and n-well regions can be required, this can require two such minimum device isolation distances, thus creating a larger layout area.
Another example of a conventional logic circuit, that may be used as a decoder, is set forth in FIG.
14
and is designated by the general reference character
1400
. Conventional logic circuit
1400
contains an input circuit
1410
, a driver circuit
1420
and a load circuit
1430
. The input circuit
1410
has three n-channel MOSFETs (N
15
-N
17
) that are configured in the same manner as the three n-channel MOSFETs (N
12
-N
14
) in the input circuit
1310
of FIG.
13
. Driver circuit
1420
of
FIG. 14
is configured in the same manner as driver circuit
1320
of FIG.
13
. Conventional logic circuit
1400
of
FIG. 14
also has a load circuit
1430
. The load circuit
1430
has a p-channel MOSFET P
9
having a source connected to VCC, a drain connected to logic evaluation node V
14
and a gate connected to GND.
In a selected state, conventional logic circuit
1400
receives inputs A
14
-C
14
which all are logic high. Thus, all three series connected n-channel MOSFETs (N
15
-N
17
) are turned on. The n-channel MOSFETs (N
15
-N
17
) are sized to have a series resistance that is significantly less than the resistance of p-channel MOSFET P
9
when the n-channel MOSFETs (N
15
-N
17
) are turned on. Therefore, when all inputs (A
14
-C
14
) are at a logic high, logic evaluation node V
14
is pulled low enough to be seen as a logic low, which is then output by driver circuit
1420
at logic output D
14
.
When any of the inputs (A
14
-C
14
) have a logic low level, at least one of the n-channel MOSFETs (N
15
-N
17
) is turned off, thus logic evaluation node V
14
is pulled high through p-channel MOSFET P
9
.
Conventional logic circuit
1400
of
FIG. 14
has a smaller input capacitance than the logic circuit
1300
of FIG.
13
. However, due to the need keep the ratio between the impedance of p-channel MOSFET P
9
and the impedance of series n-channel MOSFETs (N
15
-N
17
) low, p-channel MOSFET P
9
will typically be a relatively weak device. Thus, the pull-up speed of logic evaluation node V
14
is slow, which can adversely delay the rising edge of logic output D
14
. Conversely, if the p-channel MOSFET P
9
is made stronger, then the pull-down speed of logic evaluation node V
14
can become slow.
Conventional logic circuit
1400
of
FIG. 14
can also have the same current consumption and trip-point problems due to the rail-to-rail output of inverter INV
14
as conventional logic circuit
1300
of FIG.
13
.
Another example of a conventional logic circuit, that may be used as a decoder, is set forth in FIG.
15
and is designated by the general reference character
1500
. The conventional logic circuit
1500
contains an input circuit
1510
, a driver circuit
1520
and a load circuit
1530
. In conventional logic circuit
1500
, driver circuit
1520
and load circuit
1530
are constructed and operate generally in the same manner as driver circuit
1420
and load circuit
1430
in conventional logic circuit
1400
of FIG.
14
.
Input circuit
1510
contains two n-channel MOSFETs (N
18
and N
19
) connected in series between logic determination node V
15
and input C
15
. N-channel MOSFETs (N
18
and N
19
) receive inputs A
15
and B
15
, respectively, at their gates.
In a selected state, conventional logic circuit
1500
receives inputs A
15
and B
15
, which are logic high, and input C
15
which is at a logic low. Thus, both series connected n-channel MOSFETs (N
18
and N
19
) are turned on and pass the logic low level of input C
15
to logic evaluation node V
15
. N-channel MOSFETs (N
18
and N
19
) are sized to have a series resistance that is significantly less than the resistance of p-channel MOSFET P
10
when n-channel MOSFETs (N
18
and N
19
) are turned on. Therefore, when in a selected state, logic evaluation node V
15
is pulled low enough to be seen as a logic low which is then output by driver circuit
1520
at logic output D
15
.
In a worst case select to deselect transition, one of inputs (A
15
or B
15
) changes to logic low le

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