Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2008-01-08
2008-01-08
Nguyen, Linh (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000
Reexamination Certificate
active
07317330
ABSTRACT:
A particular embodiment of the present invention provides a shared-LUT logic circuit that provides the functionality of two (n+1)LUT logic circuits without requiring approximately twice the resources of two nLUT circuits. In some embodiments, a shared-LUT logic circuit is provided that can be configured to operate in multiple modes including, for example, an nLUT mode, an (n+1)LUT mode, and other modes.
REFERENCES:
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5295090 (1994-03-01), Hsieh et al.
patent: 5349250 (1994-09-01), New
patent: 5359242 (1994-10-01), Veenstra
patent: 5359468 (1994-10-01), Rhodes et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5436575 (1995-07-01), Pedersen et al.
patent: 5481206 (1996-01-01), New et al.
patent: 5481486 (1996-01-01), Cliff et al.
patent: 5483478 (1996-01-01), Chiang
patent: 5485103 (1996-01-01), Pedersen et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5500608 (1996-03-01), Goetting et al.
patent: 5523963 (1996-06-01), Hsieh et al.
patent: 5546018 (1996-08-01), New et al.
patent: 5629886 (1997-05-01), New
patent: 5631576 (1997-05-01), Lee et al.
patent: 5672985 (1997-09-01), Lee
patent: 5675262 (1997-10-01), Duong et al.
patent: 5724276 (1998-03-01), Rose et al.
patent: 5761099 (1998-06-01), Pedersen
patent: 5818255 (1998-10-01), New et al.
patent: 5825662 (1998-10-01), Trimberger
patent: 5889411 (1999-03-01), Chaudhary
patent: 5898318 (1999-04-01), Pedersen
patent: 5898319 (1999-04-01), New
patent: 5898602 (1999-04-01), Rothman et al.
patent: 5905385 (1999-05-01), Sharpe-Geisler
patent: 5909126 (1999-06-01), Cliff et al.
patent: 5920202 (1999-07-01), Young et al.
patent: 5926036 (1999-07-01), Cliff et al.
patent: 5999016 (1999-12-01), McClintock et al.
patent: 6021423 (2000-02-01), Nag et al.
patent: 6051992 (2000-04-01), Young et al.
patent: 6107827 (2000-08-01), Young et al.
patent: 6118300 (2000-09-01), Wittig et al.
patent: 6154052 (2000-11-01), New
patent: 6154053 (2000-11-01), New
patent: 6154055 (2000-11-01), Cliff et al.
patent: 6157209 (2000-12-01), McGettigan
patent: 6184707 (2001-02-01), Norman et al.
patent: 6191610 (2001-02-01), Wittig et al.
patent: 6191611 (2001-02-01), Altaf
patent: 6201408 (2001-03-01), Skahill et al.
patent: 6236229 (2001-05-01), Or-Bach
patent: 6288568 (2001-09-01), Bauer et al.
patent: 6288570 (2001-09-01), New
patent: 6294928 (2001-09-01), Lytle et al.
patent: 6297665 (2001-10-01), Bauer et al.
patent: 6323682 (2001-11-01), Bauer et al.
patent: 6380759 (2002-04-01), Agrawal et al.
patent: 6400180 (2002-06-01), Wittig et al.
patent: 6414514 (2002-07-01), Heile
patent: 6501296 (2002-12-01), Wittig et al.
patent: 6556042 (2003-04-01), Kaviani
patent: 6744278 (2004-06-01), Liu et al.
patent: 6747480 (2004-06-01), Kaptanoglu et al.
E. Ahmed et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density”, FPGA '2000 Monterey Ca, pp. 3-12, no month.
D. Cherepacha et al., “DP-FPGA: An FPGA Architecture Optimized for Datapaths”, VLSI Design 1996, vol. 4, No. 4, pp. 329-343.
S. Kaptanoglu et al., “A new high density and very low cost reprogrammable FPGA architecture”, FPGA 99 Monterey Ca, pp. 3-12. No date.
J. Rose et al., “Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency”, J. of Solid-State circuits, vol. 25, No. 5, Oct. 1990, pp. 1217-1224.
J. L. Kouloheris et al., “FPGA Area versus Cell Granularity-Lookup Tables and PLA Cells”, FPGA '92, pp. 9-14. No date.
“FLEX 8000 Programmable Logic Device Family”, Altera Corp. Jun. 1999, ver. 10.01, pp. 349-364.
“FLEX 10K Embedded Programmable Logic Device Family”, Altera Corp. mar. 2001, ver. 4.1, pp. 1-28.
“Flex 6000 Programmable Logic Device Family”, Altera Corp., Mar. 2001, ver. 4.1, pp. 1-17.
“Mercury Programmable Logic Device Family”, Altera Corp., Mar. 2002, ver. 2.0, pp. 1-34.
“APEX 20K Programmable Logic Device Family”, Altera Corp., Feb. 2002, ver. 4.3, pp. 1-29.
“Virtex.TM.-II Platform FPGAS: Detailed Description”, XILINX, Advance Product Specification, v2.11, Dec. 6, 2002, 40 pgs.
“Stratix FPGA Family Data Sheet”, Altera Corp., Dec. 2002, Preliminary Information, pp. 11-19.
Altera Corporation
Beyer & Weaver, LLP
Nguyen Linh
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