Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-12-04
2004-03-30
Tan, V. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S090000, C326S056000, C710S100000, C710S120000, C375S219000, C375S213000
Reexamination Certificate
active
06714051
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a logic circuitry-implemented bus buffer. Particularly, this invention relates to a bus buffer having several buffers provided at least at input and output stages with internal circuitry interposed therebetween.
With recent dramatic development of information-processing technology, several types of bus buffers haven been introduced, which are interposed between several data buses, for relaying data signals transferred through the data buses. Data transferred through a bus at one side of the bus buffer and that through another bus at the other side of the bus buffer may be or may not be sent at the same transfer speed. Moreover, data transfer via the bus buffer may be one-way or two-way transfer between the buses at one and the other sides of the bus buffer.
Applications such as Personal Digital Assistant (abbreviated to PDA hereinafter) include many bus (signal) lines for data transfer between a central processing unit (abbreviated to CPU hereinafter) in logic-circuit system and peripheral devices connected to busses in tree structure. Peripheral devices applicable to this type of application are classified into a device group (called high-speed accessible device group) including devices such as synchronous dynamic random access memories (abbreviated to SDRAM hereinafter) and another device group (called low-speed accessible device group) including devices accessible at low speed such as connectors for connection of external peripheral devices, and nonvolatile memories.
When all of the peripheral devices are driven by CPU, not only the high-speed accessible device group but also the low-speed accessible device group are driven, thus increasing power consumption which depends on device input capacity, etc. Provided for solving such a problem are usually high-speed buses for high-speed access use and low-speed buses for low-speed access use, and also bus buffers for connecting the high- and low-speed buses.
It is a well-known power-saving measurement for hand-held devices to interpose a bus buffer between high- and low-speed buses for data transfer like explained above for lowering total power consumption in application such as PDA. This measurement deactivates the low-speed accessible device group through a bus buffer while the high-speed accessible devices such as SDRAMs are being accessed, thus achieving low power consumption.
FIG. 41
is a block diagram showing the internal configuration of a well-known bus buffer
10
to which off-the-shelf bus buffer devices are applicable. The bus buffer
10
shown in
FIG. 41
is equipped with a controller
11
for generating several control signals of different logic levels in response to an input/output command signal *OE from CPU and a direction-indicating signal DIR, terminals A
1
to An for data transfer with CPU through high-speed accessing buses, terminals B
1
to Bn for data transfer with a low-speed accessible device group through low-speed accessing buses, and several operators
12
for logic operation with specific internal circuitry provided between the terminals A
1
to An and B
1
to Bn.
The sign “*” indicates a logic-level-inverted signal. For example, the signal *OE as the input/output command signal is a signal whose logic level is an inverted-version of a signal OE. The sign OE is an abbreviation of Output Enable. The sign “n” in the terminals A
1
to An and B
1
to Bn is a positive integer.
Disclosed below for the operators
12
in
FIG. 41
is only for the operator
12
provided between the terminals A
1
and B
1
because all of the operators
12
have the same circuit configuration.
The operator
12
is equipped with a first-directional-signal processor including a first input buffer
13
made up of an inverter INV
1
for accepting a signal from the terminal A
1
; an A/B-internal circuit
14
made up of an inverter INV
2
for signal processing in a direction from the terminals A
1
to B
1
(called a first direction); and a first output buffer
15
for outputting a signal from the A/B-internal circuit
14
to the terminal B
1
, having a NAND-logic circuit NAND
1
, a NOR-logic circuit NOR
1
, a P-channel transistor P
1
, and an N-channel transistor N
1
.
The operator
12
is equipped further with a second-directional-signal processor including a second input buffer
16
made up of an inverter INV
3
for accepting a signal from the terminal B
1
; a B/A-internal circuit
17
made up of an inverter INV
4
for signal processing in a direction from the terminals B
1
to A
1
(called a second direction); and a second output buffer
18
for outputting a signal from the B/A-internal circuit
17
to the terminal A
1
, having a NAND-logic circuit NAND
2
, a NOR-logic circuit NOR
2
, a P-channel transistor P
2
, and an N-channel transistor N
2
.
All of the terminals A
1
to An and B
1
to Bn are input and also output terminals. Input via a terminal *OE is the input/output command signal *OE for switching the bus buffer
10
between a signal-output mode and a high-impedance state at the input and output terminals. Input via a terminal DIR is the direction-indicating signal DIR for switching the bus buffer
10
for input/output directions. Disclosed next is an operation of the bus buffer
10
shown in FIG.
41
.
The controller
11
in
FIG. 41
generates signals *AG, AG, *BG and BG in response to the input/output command signal *OE and the direction-indicating signal DIR input via the terminals *OE and DIR, respectively. It is assumed that the signal *OE is at a low level whereas the signal DIR at a high level so that a signal is allowed to be input via the terminal A
1
and output via the terminal B
1
. The signal input via the terminal A
1
is then transferred to the transistors P
1
and N
1
via the inverter INV
1
of the first input buffer
13
, the inverter INV
2
of the A/B internal circuit
14
, and NAND
1
and NOR
1
of the first output buffer
15
, and output via the terminal B
1
.
The signal at the terminal B
1
is not only output but supplied to one of two terminals of NAND
2
and also NOR
2
of the second output buffer
12
via INV
3
of the second input buffer
16
and INV
4
of the B/A internal circuit
17
from a node connected to the terminal B
1
, thus these logic circuits are inevitably activated. A gate signal to the transistor P
2
is, however, set at a high level whereas that to the transistor N
2
is set at a low high level due to a low level for the signal BG whereas a high level for the signal *BG. The transistors P
2
and N
2
of the second output buffer
18
are thus turned off, so that no signals will be output via the terminal A
1
.
The bus buffer
10
, however, consumes power due to unwanted currents passing through the activated logic circuits. TABLE 1 in
FIG. 42
shows logic levels at the terminals A
1
and B
1
and modes of the respective circuits. It is indicated in TABLE 1 that the second-directional-signal processor is in operation even when a signal is transferred in the first direction whereas the first-directional-signal processor is in operation even when a signal is transferred in the second direction. Moreover, even when the first and second output buffers
15
and
18
are out of operation, the NAND- and NOR-logic circuits at the anterior stage to these output buffers are performing logical operations.
Furthermore, signals input to both terminals A
1
and B
1
simultaneously activate all of the first input buffer
13
, the A/B-internal circuit
14
, the second input buffer
16
, and the B/A-internal circuit
17
, thus causing high power consumption. This will happen even when the terminals A
1
and B
1
are in the high-impedance state (*OE=H), irrespective of the logic level of the signal DIR.
A first bus-hold circuit
19
a
and a second bus-hold circuit
19
b
enclosed in a dot-line block are provided for solving the problem discussed above. The bus-hold circuit
19
a
is made up of two inverters connected between the first output buffer
15
and the terminal B
1
. The bus-hold circuit
19
b
is made up of two inverters
Fujii Toru
Kinugasa Masanori
Mizuta Masaru
Takiba Akira
Tsukazaki Takumi
Kabushiki Kaisha Toshiba
Tan V.
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