Logic circuit using bipolar complementary metal oxide semiconduc

Details Logic circuit using bipolar complementary metal oxide semiconduc Logic circuit using bipolar complementary metal oxide semiconduc

1989-12-19

1990-10-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

36518909, 365208, G11C 700

Patent

active

049611704

ABSTRACT:
A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage. As a result the turning OFF of the p-channel MOS transistor is guaranteed due to the improved marginal voltage.

REFERENCES:
patent: 4829479 (1989-05-01), Mitsumoto et al.
patent: 4906868 (1990-03-01), Maki et al.

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