Logic circuit, timing generation circuit, display device,...

Details Logic circuit, timing generation circuit, display device,... Logic circuit, timing generation circuit, display device,...

2006-10-24

2006-10-24

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C345S099000, C327S295000

Reexamination Certificate

active

07126376

ABSTRACT:
When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit15with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

REFERENCES:
patent: 6914956 (2005-07-01), Kawasaki et al.
patent: 2001/0043086 (2001-11-01), Idei et al.
patent: 63-85599 (1988-04-01), None
patent: 4-195192 (1992-07-01), None
patent: 2001-265289 (2001-09-01), None
patent: 2002-116424 (2002-04-01), None

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