Logic circuit optimizing method, logic circuit optimizing...

Details Logic circuit optimizing method, logic circuit optimizing... Logic circuit optimizing method, logic circuit optimizing...

2006-12-05

2006-12-05

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07146582

ABSTRACT:
A dividing flip-flop FF2is inserted in a cluster C of which the cluster length exceeds a predetermined cluster length. The flip-flop inserted cluster C is re-clustered, generating subdivided clusters C1and C2. Therefore, the degree of freedom is increased in allocating clusters to a variable logic element such as an FPGA in a logical emulation device.

REFERENCES:
patent: 5452239 (1995-09-01), Dai et al.
patent: 5682321 (1997-10-01), Ding et al.
patent: 6618834 (2003-09-01), Takeyama et al.
patent: 2000-36737 (2000-02-01), None

Affiliated with

Also associated with

Rating

Logic circuit optimizing method, logic circuit optimizing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic circuit optimizing method, logic circuit optimizing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic circuit optimizing method, logic circuit optimizing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3717053