Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-16
2004-03-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C326S037000, C326S038000, C326S041000, C326S047000
Reexamination Certificate
active
06701500
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a logic circuit module having excellent area efficiency and capable of representing a large number of logics, a method for designing a semiconductor integrated circuit using such a logic circuit module, and a semiconductor integrated circuit.
In an FPGA (Field Programmable Gate Array), a device is first manufactured in such a form that can be used for general purposes, so that a desired circuit operation is implemented by writing data to storage elements incorporated in advance into the device or blowing fuses.
In general, a gate array is produced in advance up to a transistor portion, so that a desired circuit operation is implemented using all wiring layers. However, there is also a short-term gate array in order to implement a desired circuit in a shorter period. In the short-term gate array, not all of the wiring layers are produced in advance. Instead, some of the wiring layers are produced in advance, so that a desired circuit is formed using only the remaining wiring layers.
Moreover, in a cell base IC (Integrated Circuit), correction macro cells are incorporated in advance in order to quickly handle any erroneous circuit design found in the manufactured cell base IC. Thus, when the necessity for correction arises, only the wiring layers are corrected using the correction macro cells.
Such an FPGA and short-term gate array have a small amount of individually modifiable wiring resources for forming a semiconductor integrated circuit implementing a desired operation. Therefore, not a small unit like a transistor but a logic module capable of implementing a large number of logics by a single unit is used as a base unit for implementing a logic, in order to reduce the amount of individually modifiable wirings. A method for designing a semiconductor integrated circuit in such a conventional FPGA and short-term gate array will now be described in connection with
FIGS. 16A and 16B
. Conventionally, as shown in
FIG. 16A
, a multiplicity of 4-1 multiplexers M
13
are used as logic circuit modules in order to form a logic circuit in such a form that can be used for general purposes. Each input terminal of the logic circuit module M
13
is connected to a power supply, ground or external wiring, thereby expressing a plurality of types of logic circuits.
FIG. 16B
shows an example of a NAND logic implemented with the logic circuit module M
13
. In
FIG. 16B
, input terminals TI
1311
, TI
1312
and TI
1313
are connected to a power supply, an input terminal TI
1314
is grounded, and input terminals TI
1315
and TI
1316
are respectively connected to external input terminals A
13
and A
14
. An output terminal TO
1311
is connected to an external output terminal Y
13
. Thus, a NAND output of the external input terminals A
13
and A
14
is output to the external output terminal Y
13
.
A conventional implementation method in which macro cells are incorporated in advance for correction on the cell base IC will now be described in connection with
FIGS. 13A
to
13
C.
FIG. 13A
shows an uncorrected, original circuit. In this circuit, an OR logic circuit C
314
obtains an OR logic of respective outputs of logic circuits C
311
, C
312
and C
313
, and applies the OR logic output to an input of a logic circuit C
315
. It is now assumed that this circuit should be corrected so as to apply an AND logic of the logic circuits C
311
, C
312
and C
313
to the input of the logic circuit C
315
instead of the OR logic.
FIG. 13C
shows an example of the circuit corrected using NAND macro cells incorporated in advance. The dashed lines in the figure indicate a corrected portion. In this example, four NAND macro cells are used for correction.
In the conventional FPGA and short-term gate array, the logic circuit module M
13
of
FIGS. 16A and 16B
is capable of representing all of two-input logic circuits, but has a larger area than that of an individually implemented two-input logic circuit. In particular, a single logic circuit module is required even if only a basic gate is necessary. This results in extremely disadvantageous area efficiency in the case of a semiconductor integrated circuit that merely requires a large number of basic gates. Thus, the resultant semiconductor integrated circuit has a large size. A semiconductor integrated circuit for digital signal processing uses a large number of adders as its circuit portion. In designing such a semiconductor integrated circuit, the adders cannot be efficiently implemented in terms of the area. Moreover, in the case of a semiconductor integrated circuit using a large number of at least three-input logic circuits, a desired semiconductor integrated circuit can be reduced in size with improved area efficiency if the at least three-input logic circuits can be implemented with a logic circuit module. In fact, however, the logic circuit module M
13
can implement only a small number of types of at least three-input logic circuits. Therefore, the resultant semiconductor integrated circuit has an extremely large size.
Moreover, in the correction of a cell base IC, a portion to be corrected of a designed semiconductor circuit cannot be predicted, and NAND macro cells to be incorporated in advance must be distributed all over the semiconductor circuit. Accordingly, a long wiring length is likely to be required for partial correction, and the number of wiring layers to be modified for correction is likely to be increased. Macro cells to be incorporated in advance normally use basic gates, and therefore a large number of wiring layers are required for correction. As a result, even a slight increase in circuit scale to be corrected makes the correction difficult.
SUMMARY OF THE INVENTION
It is an object of the present invention to improve the structure of a logic circuit module so as to increase the area efficiency of the logic circuit module when implementing various logic gates in an FPGA and a short-term gate array, and thus reduce the size of the resultant semiconductor integrated circuit. It is another object of the present invention to reduce the wiring length for correction by using improved logic circuit modules as macro cells to be incorporated in advance in preparation for correction of a cell base IC. It is still another object of the present invention to reduce the number of wiring layers to be modified for correction so as to enable correction to be made in an excellent manner even if the circuit scale to be corrected is somewhat increased.
In order to achieve these objects, the present invention enables a plurality of logic functions to be represented with a single logic circuit module, and also enables a half adder to be formed with a single logic circuit module.
More specifically, a logic circuit module according to the present invention is characterized in that it comprises a plurality of input terminals, a plurality of output terminals, and a plurality of logic elements provided between the plurality of input terminals and the plurality of output terminals, the plurality of input terminals are each connected to an external signal line, a power supply or a ground so as to implement a plurality of desired logic functions, and at least two of the implemented plurality of logic functions are such that a potential state of an output terminal corresponding to one of the logic functions is not affected by a potential state of an input terminal corresponding to the other logic function.
The logic circuit module according to the present invention is characterized in that at least one of the plurality of logic elements separates at least two of the implemented plurality of logic functions from each other so as to make the two logic functions independent of each other.
A logic circuit module according to the present invention is characterized in that it comprises first to seventh input terminals, first and second output terminals, and first to third 2-1 multiplexers, the first 2-1 multiplexer has its two signal terminals respectively connected to the first and second input terminals, an
Matsushita Electric - Industrial Co., Ltd.
Siek Vuthe
LandOfFree
Logic circuit module, method for designing a semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic circuit module, method for designing a semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic circuit module, method for designing a semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3274990