Logic circuit having a test data scan circuit

Electricity: measuring and testing – Plural – automatically sequential tests

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324158R, G01R 3128

Patent

active

047032570

ABSTRACT:
A logic circuit having a diagnostic function is disclosed in which each of first latches for applying data to combinational circuits included in the logic circuit and/or receiving data from the combinational circuits is provided with a second latch and a selector for selecting the output of the first latch in a first mode and for selecting the output of the second latch in a second mode. In a regular operation, the output of the first latch is never transferred through the second latch, and the selector is operated in the first mode. Accordingly, the output of the first latch is supplied directly to a succeeding combinational circuit, and thus the delay caused by the second latch in the prior art can be eliminated. Although the delay caused by the selector is unavoidable, this delay can be made far smaller than the delay caused by the second latch. In a diagnostic operation, the output of the first latch is transferred through the second latch, and the selector is operated in the second mode, in order to perform the diagnostic operation stably even when data is transferred between first latches having the same phase, or the logic circuit includes a one-latch loop.

REFERENCES:
patent: 4553236 (1985-11-01), Zario et al.
"Testing of LSI Logic Circuits Containing Imbedded Shift Arrays"; IBM Technical Disclosure; vol. 20, No. 10; Mar. 1978; pp. 4021-4022.

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