Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1993-11-03
1995-01-17
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326112, 326 21, H03K 1920
Patent
active
053828445
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a logic circuit with differential cascode voltage logic.
A logic circuit of this type is reproduced, for example, in the publication by T. Meng et al. entitled "Design of Clock-Free Asynchronous Systems for Real-Time Signal Processing" in the Digest of Technical Papers, pages 2532 to 2535 for the conference IEEE ICCAD 89. This circuit has a logic circuit with two logic blocks which are formed in each instance of n-channel transistors and in which circuit in each instance one part of a logic block is coupled back via an invertor with the gate of a precharging transistor connected to this logic block, in order in each instance to assure the output voltage of the logic blocks on a steady basis until such time as valid data cause a potential change at the output of the logic circuit.
The European Patent Application bearing the publication number 0,147,598 A1 discloses furthermore a system with differential cascode voltage switching logic, in which system a first logic block and a second logic block each have a switch, the switch of the first logic block always being closed when the switch of the second logic plug is open and vice versa, and the switch of the second logic plug being driven in a manner complementary to the switch of the first logic block.
SUMMARY OF THE INVENTION
The object of the invention is to provide a logic circuit for asynchronized circuits which offers a greater interference resistance and a lower power loss with the simultaneous use of conventional CMOS logic blocks.
According to the invention, this object is achieved by a logic circuit with differential cascode voltage logic in which a plurality of input lines are connected to a first logic block and also to a second logic block. Depending on signals on the input lines, either a first output of the first logic block is switched through to a second output of the first logic block, in this case a first output of the second logic block being separated from a second output of the second logic block, or the first output of the first logic block is separated from the second output of the first logic block, in this case the first output of the second logic block being switched through to the second output of the second logic block. The first output of the first logic block is connected to each first connection of a first transistor and a second transistor of a first pair of precharging transistors. The second output of the first logic block is connected to a first connection of a charging transistor. The first output of the second logic block is connected to each first connection of a first transistor and a second transistor of a second pair of precharging transistors. The second output of the second logic block is connected to a first connection of a charging transistor. A gate of the first transistor of the first pair of precharging transistors and a gate of the charging transistor connected to the first logic block is directly connected to a request input. At a first logic level at the request input only the transistors of the pairs of precharging transistors are conductive and all charging transistors which are present are non-conductive. At the second logic level at the request input only all charging transistors which are present are conductive and the transistors of the pairs of precharging transistors are non-conductive. A gate of the second transistor of the first pair of precharging transistors is connected to an output of a first feedback invertor. A gate of the second transistor of the second pair of precharging transistors is connected to an output of a second feedback invertor. The first output of the first logic block is connected to a first input of a logic link and the first output of the second logic block is connected to a second input of the logic link. An output of the logic link represents a complete message output. A second connection of the first transistor and second transistor of the first pair of precharging transistors has applied to it a supply voltage and a
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patent: 5272397 (1993-12-01), Chen et al.
"Design of Clock-Free Asynchronous Systems for Real-Time Signal Processing" by T. Meng et al, Digest of Technical Papers, IEEE ICCAD, (1989), pp. 2532-2535.
Sanders Andrew
Siemens Aktiengesellschaft
Westin Edward P.
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