Logic circuit evaluation using sensing latch logic

Details Logic circuit evaluation using sensing latch logic Logic circuit evaluation using sensing latch logic

2000-02-28

2002-04-16

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06374393

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic circuit in a CMOS semiconductor integrated circuit etc., more particularly relates to a logic circuit serving as a flip-flop with an embedded logic function combining the functions of a 1-bit storage element operating in synchronization with a synchronization signal, that is, a flip-flop, and several logic gates located at its data input packaged into one unit.
2. Description of the Related Art
An integrated circuit generally performs a logical operation by a combination of logic gates and stores the results thereof in a flip-flop for use for the operation of the next cycle.
For example, structures very common in integrated circuits such as sequential circuits and pipelines are also configured by flip-flops and one or more logic gates arranged at the data input thereof.
Below, an explanation will be made of first to fourth conventional examples of a circuit comprised of a flip-flop and one or more logic gates arranged at the data input thereof.
First Conventional Example
FIG. 1
is a view of a first conventional example realizing a general structure of a flip-flop and logic gates arranged at the data input thereof by a static CMOS logic circuit
10
.
As shown in
FIG. 1
, the desired logical function is realized by a combinational logic circuit LC
11
. A logical function output F
11
thereof is supplied to a data input D of a flip-flop FF
11
.
In the flip-flop FF
11
, a value of the input D is fetched in synchronization with a synchronization signal CLK and output from a data output Q.
FIG. 2
is a circuit diagram of a transistor level of the flip-flop FF
11
.
The flip-flop FF
11
shown in
FIG. 2
is based on a master-slave type flip-flop using a CMOS transmission gate disclosed in John P. Uyemura,
CMOS LOGIC Circuit Design
, Kluwer Academic Publishers, pp. 278-281, 1999 and is being generally used at the present.
Specifically, the flip-flop FF
11
of
FIG. 2
has inverters INV
11
to INV
18
and CMOS transmission gates TMG
11
and TMG
12
.
Further,
FIG. 3
is a circuit diagram of an example of the configuration of the combinational logic circuit LC
11
.
This logic circuit LC
11
has a 2-input exclusive OR gate (EXOR) ER
11
, a 2-input exclusive negative OR gate (EXNOR) ENR
11
, and a 2-input NAND gate NA
11
.
A logic circuit LC
1
of
FIG. 3
shows a case where the logical function F=A(+){(B(+)C)·D} is realized.
Second Conventional Example
Further, the idea itself of combining the functions of a flip-flop and several logic gates located at its data input into one package has been already disclosed.
As a first example thereof, there is a PDN (pull down network) mounted type flip-flop of the AMD Co. (below, simply referred to as a “PDN-F/F”) (refer to Steven Hesley et al., “A 7th-Generation ×86 Microprocessor”,
ISSCC DIgest of Technical Papers
, pp. 92-93, February 1999, or Alisa Scherer et al., “An Out-of-Order Three-Way Superscalar Multimedia Floating-Point”,
ISSCC Digest of Technical Papers
, pp. 282-283, February 1999).
FIG. 4
is a circuit diagram of the general configuration of a PDN-F/F, and
FIG. 5
is a circuit diagram of a concrete example of the configuration of a PDN-F/F logic circuit mounting a logical function of one multiplexer.
The PDN-F/F logic circuit
20
is configured by a dynamic circuit unit
21
comprising p-channel MOS (PMOS) transistors PT
21
and PT
22
and n-channel MOS (NMOS) transistors NT
11
to NN
13
and by a static circuit unit
22
comprising inverters INV
21
and INV
22
with inputs and outputs connected with each other and configuring a latch and an output use inverter INV
23
.
PDN is an abbreviation of a “pull down network” as mentioned above and is what is generally referred to as an NMOS single-rail type logic tree
23
.
In this system, the dynamic circuit unit
21
evaluates the logic, and the value thereof is held by the latch of the static circuit unit
22
.
The characterizing feature of the PDN-F/F logic circuit
20
resides in that a pulsed clock PCLK to be input to the PMOS transistor PT
21
and an NMOS transistor NT
21
must be a short width pulse which is generated in synchronization with the rising of the global synchronization signal CLK.
The pulsed clock PCLK is generated by a pulse generator
24
as shown in FIG.
5
.
This pulse generator
24
is configured by an inverter INV
24
to which a clock inverted signal CLK_X is input, a PMOS transistor PT
23
and NMOS transistors NT
24
and NT
25
connected in series between a supply line of a power source voltage V
DD
and a ground and having gates to which the output of the inverter INV
24
is supplied, a 2-input NAND gate NA
21
to which a potential of a connection point of drains of the PMOS transistor PT
23
and the NMOS transistor NT
24
and an enable signal ENB are input, and a 2-input NOR gate NR
21
to which the output of the NAND gate NA
21
and the clock inverted signal CLK_X are input.
When the pulsed clock PCLK has a logic “0”, an internal node F is initialized to a logic “1”.
When the pulsed clock PCLK becomes the logic “1”, the logic is evaluated in the logic tree (PDN)
23
, and the node F changes. This change is transferred to the latch
22
a
comprising the inverters INV
21
and INV
22
through a dynamic inverter configured by the PMOS transistor PT
22
and NMOS transistors NT
23
and NT
24
. During this period, the input signal must not change.
The important thing in the PDN-F/F logic circuit
20
is that the time during which the pulsed clock PCLK becomes the logic “0” is precisely controlled.
This time must be the minimum time long enough for a change of the potential of the node F from the logic “1” to the logic “0”.
If it is too short, the potential ends up returning to logic “1” again while F does not sufficiently change to the logic “0”, so the logic cannot be correctly evaluated. If it is too long, however, the time during which the input signal cannot change becomes long.
As the times during which the input must not change at a time of operation, even in a general flip-flop, there are a set-up time and a hold time. It generally is regarded that a shorter time means better performance.
The time during which the pulsed clock PCLK becomes the logic “1” is directly related to the set-up time and the hold time in the PDN-F/F logic circuit
20
, so a shorter width of the pulsed clock PCLK is preferred.
The characterizing feature of the pulse generator
24
shown in
FIG. 5
generating the pulsed clock PCLK resides in that an adequate width of the pulsed clock PCLK is obtained by the NMOS transistors NT
24
and NT
25
.
When the PDN, that is, the logic tree
23
, becomes three NMOS's in size, that is, if another NMOS transistor is added in series in addition to the NMOS transistors NT
24
and NT
25
, it becomes possible to generate three NMOS's worth of delay in the pulse generator
24
.
It is considered that the main object of the PDN-F/F logic circuit
20
resides in the realization of a high speed logic circuit.
In general, a circuit realized by a dynamic logic circuit is higher in speed than one realized by a static logic circuit.
Further, in the PDN-F/F logic circuit
20
, the master latch and the logic tree are combined with the aim of shortening the set-up time and the hold time relating to the input terminal of the logical functions.
Third Conventional Example
As a second example of the idea of combining the functions of a flip-flop and several logic gates located at its data input into one package, a sense amplifier-based flip-flop (hereinafter simply referred to as an “SA-F/F”) may be mentioned (see Borivoje Nikolic et al., “Sense Amplifier-Based Flip-Flop”,
ISSCC Digest of Technical Papers
, pp. 282-283, February 1999 or R. Stephany et al., “A 200 MHZ 32 b 0.5 W CMOS RISC Microprocessor”,
ISSCC Digest of Technical Papers
, pp. 238-239, February 1998).
FIG. 6
is a circuit diagram of the general configuration of an SA-F/F logic circuit, while
FIG. 7
is a circuit diagram of a concrete example of the configuratio

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