Logic circuit design method, computer-readable recording...

Details Logic circuit design method, computer-readable recording... Logic circuit design method, computer-readable recording...

2007-11-27

2007-11-27

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11165344

ABSTRACT:
A logic circuit design method for use in a logic circuit having a hierarchical structure including an instance, a first block, and a second block is disclosed. The logic circuit design method includes the steps of reading information about the logic circuit, moving an instance which has a signal connection and a first hierarchical port connected thereto from a first block to a second block in accordance with the read information, creating a second hierarchical port in accordance with the movement of the instance, and disconnecting the instance from the first hierarchical port and connecting the instance to the second hierarchical port while maintaining the signal connection to the instance that the instance had at the time when the instance was moved from the first block to the second block.

REFERENCES:
patent: 5889677 (1999-03-01), Yasuda et al.
patent: 6035106 (2000-03-01), Carruthers et al.
patent: 7073149 (2006-07-01), Knol et al.
patent: 7158924 (2007-01-01), Williams et al.
patent: 3-27474 (1991-02-01), None
patent: 2003-256490 (2003-09-01), None

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