Logic circuit design method and logic circuit

Details Logic circuit design method and logic circuit Logic circuit design method and logic circuit

2001-02-05

2003-02-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S016000, C326S039000, C326S040000

Reexamination Certificate

active

06518788

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a logic circuit including a plurality of scan flip-flop circuits, and a logic circuit design method for designing the same, and more particular to a logic circuit design method for regulating a clock skew of a scan path.
2. Description of the Related Arts
In designing the logic circuit, the scan path is constituted by tandem-connecting a plurality of flip-flops included in the logic circuit, and a scan path test for verifying operation of the logic circuit has been performed in the prior art (each flip-flop configuring the scan path is referred to as a scan flip-flop, and hereinafter described as a scan FF). The scan FF has scan terminals for the scan path (a scan input terminal (SI) and a scan output terminal (SO)), and the scan output terminal (SO) of each scan FF is connected to the scan input terminal (SI) of the next scan FF, thereby configuring the scan path.
At this time, the logic circuit has a plurality of different clock sources, and when it is connected to the scan FF operating by mutually differing clock sources, a clock skew occurs, and a hold time of the scan FF is sometimes not satisfied.
Furthermore, since a combination circuit does not exist between the scan FFs in the scan path, a propagation speed of data is fast, and the hold time is not sometimes met even between the scan FFs operating in the same clock source. However, the clock skew based on the same clock source is generally relatively smaller than the clock skew based on the different clock source.
FIG. 8
are diagrams for explaining the clock skew in the scan path. In
FIG. 8A
, a scan FF
1
and scan FF
3
are operated by a clock CK
1
, and a scan FF
2
is operated by a clock CK
2
. In
FIG. 8B
, in the case where there is no skew in the clock CK
1
and clock CK
2
, data
1
to be input to a scan input terminal SI of the scan FF
2
meet a hold time (period A) of the scan FF
2
. On the other hand, when there is a skew between the clock CK
2
and clock CK
1
, a signal to be input to the scan input terminal (SI) of the scan FF
2
does not satisfy the hold time (period B) of the scan FF
2
.
Such the clock skews are regulated conventionally by the following technique:
(1) A delay element such as a buffer is inserted into between the scan FFs in which the clock skew occurs.
(2) All the scan FFs configuring the scan path are set as the scan FF including the delay circuit.
However, the above technique has the following problems: Namely, in the case where the above (1) delay element is inserted, in order to regulate the relatively large clock skew such as the clock skew based on the different clock source, a buffer using relatively frequently the number of basic cells (unit indicating a scale of the logic circuit) is necessary. When the many basic cells are allocated to the logic element which is used only for regulation of the clock skew and has no connection with operations of the logic circuit, this prevents integration of the logic circuit, unpreferably.
For example, in a clock cycle 8 ns, in order to generate a delay of half-cycle 4 ns (4000 ps) of the clock cycle, it is necessary that the buffer using about 20 basic cells (hereinafter called BC) is inserted into between the scan FFs.
However, at this time, when utilizing the scan FFs including the delay circuit generating a delay of the half-cycle instead of the buffer, it is possible to regulate the clock skew by using the less number of basic cells. Specifically, in the case where the clock skew occurs between a first scan FF and a second scan FF which scan input terminal (SI) is connected to a scan output terminal (SO) of the first scan FF, the first scan FF is changed into a scan FF including a delay circuit. For example, in the case where the number of basic cells of the normal scan FF not integral with the delay circuit is, for example, 8BC, and the number of basic cells of the scan FF including the delay circuit is, for example, 10BC, the clock skew is regulated by additional use of 2BC.
On the other hand, in the case where the scan FFs configuring the above (2) scan path are all changed to the scan FFs including the delay circuit, as compared with the case where the clock skew between the two scan FFs is relatively small and the scan FFs are changed to the scan FFs including the delay circuit, it is occasionally possible to regulate by insertion of the buffer of the smaller basic cells. For example, as compared with the case where the normal scan FFs of 6 BC are changed to, for example, the scan FFs including the delay circuit of 10 BC, for example, in the case where the buffer of 1 BC is inserted, it is possible to regulate the clock skew by use of the less basic cells. In particular, as most of the clock skews between the scan FFS configuring the scan path are relatively small skews, in order to regulate the clock skew, it is inefficient to change all the scan FFS to the scan FFS including the delay circuit.
In this manner, it is preferable that the scan FFS including the delay circuit are utilized for regulating the relatively large clock skew, and it is preferable that the buffer is inserted for regulating the relatively small clock skew. By so doing, it is possible to minimize the number of basic cells to be used for regulating the clock skew.
However, in the prior art, in response to a magnitude of the clock skew as described above, the buffer and the scan FF including the delay circuit have not been used properly.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a logic circuit design method which judges a magnitude of a clock skew generating between scan FFS configuring a scan path and applies optimal clock skew regulating means in response to the magnitude.
Furthermore, it is another object of the present invention to provide a logic circuit in which the clock skew of the scan path is regulated by use of the basic cells as few as possible.
In order to attain the above objects, according to the present invention, the plurality of flip-flops included in the logic circuit are grouped by the clock source, thereby judging a relatively large part of the clock skew. Namely, the relatively large clock skew generates between the scan flip-flop belonging to a certain group connected by the scan path and the scan flip-flop belonging to another group. Specifically, as the last scan flip-flop each group is connected to the scan flip-flop belonging to another group, the scan flip-flop including the delay circuit is applied to the last scan flip-flop of each group, whereby it is possible to regulate the relatively large clock skew by use of the less number of basic cells by insertion of the buffer. Furthermore, in the relatively small part of the clock skew, the clock skew is regulated by insertion of the buffer. In this manner, the scan flip-flop including the delay circuit and buffer are used properly corresponding to a magnitude of the clock skew, so that as compared with the case where all the scan FFs are set as the scan flip-flops including the delay circuit, or the case where all the clock skews are regulated by insertion of the buffer, it is possible to lessen the number of basic cells to be used for regulating the clock skews, and to increase integration in the logic circuit.
In order to attain the above objects, according to a first aspect of the present invention there is provided a logic circuit design method for designing a logic circuit having a plurality of flip-flops, comprising the steps of:
grouping the plurality of flip-flops into at least a group of the flip-flops operating based on a first clock; and a group of the flip-flops operating based on a second clock;
structuring a scan path by setting the plurality of flip-flops respectively as scan flip-flops, and by tandem-connecting scan terminals provided in each scan flip-flop; and
applying a scan flip-flop including a delay circuit for delaying an output of the scan terminal to the scan flip-flop which operates at the first clock and is connected to

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