Logic circuit design method and cell library for use therewith

Details Logic circuit design method and cell library for use therewith Logic circuit design method and cell library for use therewith

2001-07-16

2003-01-07

Tran, M. T (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06505322

ABSTRACT:

PRIORITY TO FOREIGN APPLICATIONS
This application claims priority to Japanese Patent Application No. P2000-274986.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of improving the delay characteristics of existing logic circuits, thereby providing logic circuits operating at a faster speed, and a method of synthesizing high-speed logic circuits by using a Hardware Description Language (HDL) such as Verilog or VHDL.
2. Description of the Background
Many study results about methods for making logic circuits operate at faster speeds by modifying existing logic circuits have been published.
The maximum operating speed of a circuit depends upon the delay of a path called a critical path for which the longest delay is observed when a signal from the input terminal of the circuit is carried across the path to the output terminal. Thus, it is important to reduce the critical path delay. For example, in IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 6, pp. 106201981 (1987)(“reference 1”), a method for increasing the speed of a circuit is described which applies the following two methods to all gates constituting a critical path:
(1) The first method optimizes the gate drive capability (inserting a buffer as required), whereby the delay per gate is reduced for all gates along the critical path.
(2) The second method applies circuit restructuring based on Boolean equations to each circuit comprising a plurality of gates along the path, thereby reforming the entire circuit into one with shorter depth of the critical path, that is, the path comprises a decreased number of stages. In this way, the number of stages, or the depth of the critical path, can be reduced, and the path delay will decrease.
By applying the above two methods repeatedly, a logic circuit operating at a faster speed may be obtained.
In Japanese Patent Laid-Open Publication No. Hei 11-161470 (“reference 2”), a method for increasing the speed of a logic circuit utilizing a path depth reduction method based on selectors was introduced. In this method, AND gates and OR gates that constitute a logic circuit are translated into logically equivalent selectors with two inputs and one output. Thus, the logic circuit is transformed into one comprising the selectors with two inputs and one output. Then, a critical path is detected in the resulting selector-based circuit. The detected critical path is separated into sections of two selector stages, and the path depth is reduced by applying a path depth reduction pattern that transforms the two stages into a one stage path section. Finally, all selectors are converted into pass transistor selectors with two inputs and one output, each of which comprises a pass-transistor circuit. In this way, a high-speed pass-transistor circuit with the same logical function as the original logic circuit is obtained.
The reference describes a path depth reduction method based on selectors by which two stages in path sections can be reduced to one stage in any kind of circuit. Thus, path depth reduction is possible for a circuit for which it is impossible to apply such circuit transformation based on Boolean equations as described in reference 1, and a resulting increase in circuit speed may be expected. In reference 2, in fact, an example case was introduced where a logic circuit operating three times as fast as the original circuit was successfully created.
Furthermore, in Proceeding of IEEE 1998 Custom Integrated Circuits Conference, pp. 291-294, (“reference 3”), another method was introduced. In this method, after a logic circuit is replaced by the corresponding circuit comprising selectors with two inputs and one output and path depth reduction processing based on selectors is performed as in the method of reference 2, the selectors with two inputs and one output are mapped to a CMOS logic circuit consisting of AND/OR gates by an existing logic circuit synthesis tool.
According to reference 3, the depth reduction processing based on selectors is so powerful that a sufficient increase in circuit speed can be expected even if the selectors are eventually mapped again onto the CMOS logic circuit. In fact, an exemplary case was introduced where the method of reference 3 enabled the circuit to operate at double the speed of the circuit generated by the logic circuit synthesis tool alone. This method may be widely used because the mapping to a CMOS logic circuit is of general application in electronics.
SUMMARY OF THE INVENTION
The path depth reduction method based on selectors introduced in references 2 and 3 may improve performance in many cases. However, in a practical logic circuit, a plurality of paths may exist between an input terminal and an output terminal which are the starting point and the ending point of the paths. In other words, when a path from the input terminal is traced toward the output terminal, a path may be found that diverges at a gate and separates into two or more paths, and these paths may converge at another gate near the output terminal and rejoin one path to the output terminal (this path divergence and convergence will be referred to as “path looping”).
A path looping example is given in FIG.
3
. Here, a path from IN
1
to O
1
diverges at the output N
100
from S
100
and separates into two paths (N
100
→I
0
of S
101
and I
1
of S
101
), and these paths converge at S
101
and rejoin one path. This path then diverges at the output N
101
from S
101
and separates into two paths (N
101
I
0
of S
102
and I
1
of S
102
), and these paths converge at S
102
and rejoin one path.
If a critical path has such path looping and separates into a plurality of sub-paths, it is necessary to apply path depth reduction to these two or more sub-paths simultaneously to reduce the path delay. However, the path depth reduction method introduced in references 2 and 3 is effective only for a single path.
Basic path depth reduction patterns described in these references are shown as items b to e in FIG.
1
. All of these patterns, in fact, can be used only for a single critical path. If we try to apply the path depth reduction pattern of item b in
FIG. 1
to the two path stages formed by the two selectors S
101
and S
102
in the section from N
100
to O
1
of the circuit shown in
FIG. 3
, a circuit is translated as shown in
FIG. 5
where the number of stages increased from three stages to four stages. As is evident from the above, the conventional method described in references 2 and 3 is not effective for a looping critical path.
In many cases, a circuit with a looping critical path may be found. A typical case is an arithmetic circuit such as an adder. For example,
FIG. 19
shows a carry output C
3
circuit portion extracted from a circuit comprising 4-bit ripple-carry adders. In this circuit, the critical path loops in three sections (G
10
→G
11
-G
12
/G
16
→G
13
, G
13
→G
17
-G
18
/G
21
→G
22
, and G
22
→G
23
-G
24
/G
27
→G
28
). An arithmetic circuit such as an adder is essential for an LSI that must execute arithmetic operation, for example, a CPU to execute arithmetic calculation and a DSP chip for signal processing installed in mobile telephone equipment. In terms of practical applications, thus, it is very important to provide a delay reduction method that is also effective for a looping critical path.
In the method of prior art reference 3, described above, the selectors with two inputs and one output, generated after the path depth reduction processing based on selectors, are mapped onto a general CMOS logic circuit consisting of AND/OR gates by a logic circuit synthesis tool. Without considering the delay of the circuit generated after these selectors with two inputs and one output are mapped to CMOS gates, the critical path in the circuit consisting of selectors is presumed, and its depth reduction is performed. In this process, there is a possibility of reducing the number of stages, or the depth of a path, that is not critical. In the prior art reference 3, however, no con

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