Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2011-08-23
2011-08-23
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S104000, C326S112000, C326S119000
Reexamination Certificate
active
08004316
ABSTRACT:
A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The first dedicated logic terminal is connected to the outer diffusion connection of the p-type transistor, the second dedicated logic terminal is connected to the outer diffusion connection of the n-type transistor, the inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor is connected to form a common diffusion logic terminal, the high-voltage terminal is connected to the bulk connection of the p-type transistor, and the low-voltage terminal is connected to the bulk connection of the n-type transistor.
REFERENCES:
patent: 3986042 (1976-10-01), Padgett et al.
patent: 5412599 (1995-05-01), Daniele et al.
patent: 5917758 (1999-06-01), Keeth
patent: 6084437 (2000-07-01), Sako
patent: 6124736 (2000-09-01), Yamashita et al.
patent: 6185719 (2001-02-01), Sako
patent: 6486708 (2002-11-01), Yamashita et al.
patent: 7305650 (2007-12-01), Jensen
patent: 7345511 (2008-03-01), Morgenshtein et al.
patent: 2004/0130349 (2004-07-01), Morgenshtein et al.
patent: 2007/0261015 (2007-11-01), Morgenshtein et al.
Notice of Allowance Dated Dec. 17, 2009 From the US Patent and Trademark Office Re.: U.S. Appl. No. 11/826,281.
SparsØ et al. “Delay-Intensitive Multi-Ring Structures”, Interigation, the VLSI Journal, vol. 15 (3): p. 313-340, 1993. Abstract.
Al-Assadi et al. “Pass-Transistor Logic Design”, International Journal of Electronics, 70(4): 739-749, 1991.
Alidina et al. “Precomputation-Based Sequential Logic Optimization for Low Power”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4): 426-435, 1994.
Casans et al. “Circuit Provides Constant Current for ISFETs/MEMFETs”, Design Ideas, EDN, p. 164/166, 2000. Article Is Complete!
Chandrakasan et al. “Low-Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, 27(4): 473-484, 1992.
Chandrakasan et al. “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, 83(4): 498-523, 1995.
David et al. “An Efficient Implementation of Boolean Functions As Self-Timed Circuits”, IEEE Trans. on Computers, 41(1): 2-11, 1992.
Morgenshtein et al. “Asynchronous Gate-Diffusion-Input (GDI) Circuits”, ISCAS 2002 IEEE International Symposium on Circuits and Systems, p. 1-8, 2002.
Morgenshtein et al. “Gate-Diffusion Input (GDI)—A Novel Power Efficient Method for Digital Circuits: A Detailed Methodology”, 14th Annual IEEE International ASIC/SOC Conference, USA, p. 39-43, 2001.
Morgenshtein et al. “Gate-Diffusion Input (GDI)—A Technique for Low Power Design of Digital Circuits: Analysis and Characterization”, IEEE, p. I-477-I-480, 2002.
Morgenshtein et al. “Gate-Diffusion Input (GSI): A Power Efficient Method for Digital Combinatorial Circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(5): 566-581, 2002.
Ozdag et al. “High-Speed QDI Asynchronous Pipelines”, Proc. 8th Int. Symposium on Asynchronous Circuits and Systems (ASYNC'02), p. 1-10, 2002.
Yano et al. “Top-Down Pass-Transistor Logic Design”, IEEE J. Solid-State Circuits, 31(6): 792-803, 1996.
Zimmermann et al. “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, 32(7): 1079-1090, 1997.
International Preliminary Report on Patentability Dated Aug. 30, 2007 From the International Bureau of WIPO Re.: Application No. PCT/IL2006/000129.
Official Action Dated Apr. 4, 2006 From the US Patent and Trademark Office Re.: U.S. Appl. No. 10/648,474.
Official Action Dated Feb. 7, 2005 From the US Patent and Trademark Office Re.: U.S. Appl. No. 10/648,474.
Official Action Dated May 20, 2005 From the US Patent and Trademark Office Re.: U.S. Appl. No. 10/648,474.
Official Action Dated Oct. 20, 2006 From the US Patent and Trademark Office Re.: U.S. Appl. No. 10/648,474.
Office Action Dated Oct. 24, 2010 From the Israel Patent Office Re. Application No. 185323 and Its Translation Into English.
Morgenshtein et al. “Gate-Diffusion Input (GDI)—A Novel Power Efficient Method for Digital Circuits: A Design Methodology”, 14th Annual IEEE International ASIC/SOC Conference, USA, p. 39-43, 2001.
Ozdag et al. “High-Speed QDI Asynchronous Pipelines”, Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'02), p. 13-22, 2002.
Fish Alexander
Morgenshtein Arkadiy
Technion Research & Development Foundation Ltd.
Tran Anh Q
LandOfFree
Logic circuit and method of logic circuit design does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic circuit and method of logic circuit design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic circuit and method of logic circuit design will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2704807