Logic circuit and method of designing the same

Details Logic circuit and method of designing the same Logic circuit and method of designing the same

1997-03-28

1999-11-23

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 81, 326 97, 326121, H03K 19096

Patent

active

059907061

ABSTRACT:
A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An output of the logic gate 1 is an input to the logic gate 2. No level converter is arranged between the logic gates 1 and 2, and therefore, the power dissipation of the CMOS logic circuit is small. The CMOS logic circuit is designed according to a method that satisfies timing requirements and maximizes the number of logic gates that operate on the lower supply voltage (VDDL).

REFERENCES:
patent: 3778782 (1973-12-01), Kitagawa
patent: 3935474 (1976-01-01), Komarek
patent: 3943377 (1976-03-01), Suzuki
patent: 5103121 (1992-04-01), Wendell et al.
patent: 5378942 (1995-01-01), Wu et al.
patent: 5490119 (1996-02-01), Sakurai et al.
patent: 5804988 (1998-09-01), Uchida

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