Logic circuit and its forming method

Details Logic circuit and its forming method Logic circuit and its forming method

2002-10-09

2004-02-24

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S106000, C326S108000, C716S030000, C716S030000

Reexamination Certificate

active

06696864

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fast logic circuit formed using selector circuits, as well as a method for forming such the logic circuit.
2. Description of Related Art
There have been published many researches with respect to fast logic circuits so far. Many of those fast logic circuits use pass transistors.
For example, Proceeding of IEEE 1994 Custom Integrated Circuits Conference (pp.603-606) (hereafter, to be referred as document 1) has proposed a method for forming a logic circuit by combining 2-input 1-output pass transistor selectors composed of only n-channel field-effect transistors and delay time improvement buffer inverters respectively. In this case, an object fast logic circuit is successfully formed as a compact circuit provided with less transistors through the use of the characteristics of the pass transistor that can realize a complicated logic function with less transistors.
On the other hand, IEEE Journal of Solid-State Circuits (Vol.25, No.2, pp.388-395) (hereafter, to be referred to as document 2) has proposed a differential fast pass transistor logic circuit, which is referred to as a CPL (Complementary Pass transistor Logic). Just like in the document 1, the CPL logic circuit is composed of 2-input 1-output pass transistor selectors composed of only n-channel field-effect transistors and buffer inverters respectively. The most typical characteristic of the CPL is that two 2-input 1-output pass transistor selectors are always paired so as to be formed as a differential logic circuit that uses signals of both positive and negative polarities. This is different from the technology disclosed in the document 1. Such way, the CPL forms a fast logic circuit by taking advantage of the characteristics of both pass transistor circuit that can realize a complicated logic function with less transistors and differential circuit that requires no inverter for polarity matching. According to the document 2, the CPL has actually realized a full adder 2.5 times faster than a CMOS circuit.
In addition, IEEE International Solid-state Circuits Conference Digest of Technical Papers (pp.90-91, 1993) (hereafter, to be referred to as document 3) has proposed a pass transistor logic circuit referred to as a DPL (Double Pass transistor Logic). Similarly to the CPL, the DPL logic circuit is composed of differential pass transistor selectors so as to use signals of both positive and negative polarities. Unlike the CPL, however, each pass transistor selector is composed of both n-channel and p-channel field-effect transistors. In the case of the pass transistors proposed in the documents 1 and 2, each selector circuit is composed of only n-channel field-effect transistors. Thus, a voltage drop equivalent to the threshold voltage of such a transistor appears at the output of the selector circuit. Consequently, if the supply voltage is low, the circuit cannot operate fast. In the case of the DPL, each selector uses p-channel field-effect transistors together with n-channel field-effect transistors thereby avoiding such a problem of voltage drop equivalent to the threshold voltage value. Consequently, the circuit can operate fast even at a low supply voltage.
Furthermore, U.S. Pat. No. 5,040,139 (hereafter, to be referred to as document 4), U.S. Pat. No. 5,162,666 (hereafter, to be referred to as document 5), and U.S. Pat. No. 5,200,907 (hereafter, to be referred to as document 6) have disclosed methods for forming logic circuits using selectors composed mainly of pass transistor circuits referred to as a TGM circuit (Transmission Gate Multiplexer) respectively. A TGM composed mainly of pass transistor circuits can operate faster than XOR, NAND, and NOR gates composed of a CMOS circuit respectively, so a TGM based logic circuit can operate faster than any of conventional CMOS based logic circuits.
Generally, an actual large logic circuit has a plurality of paths between an input and an output respectively. Consequently, a time required until an output signal is determined (that is, a delay time of the output signal) is decided by the delay time of a (so-called critical) path among the paths, which has the largest total delay time of its elements of a transistor circuit such as a transistor, etc. In addition, if there are a plurality of output signals, the operation speed of a logic circuit is decided by the delay time of the output signal whose delay time is the largest.
Consequently, if there is even one path whose delay time is extremely large, the circuit, as a whole, cannot operate fast even when the delay times of all other paths are very small and they can operate fast. In order to form a large and fast logic circuit actually, therefore, it is very important to make the number of steps in all the paths equal by all means and avoid forming a path having an extremely large delay time when in designing the logic circuit.
In spite of such the circumstances, none of the documents described for the conventional technologies have guaranteed any method for preventing such an extremely slow path from being formed as described above, although those conventional technologies are very effective for improving the operation speed of a circuit itself. Furthermore, none of the documents 1 to 6 mentions any method for forming a logic circuit so as to make the number of steps in all its paths as equal as possible.
And, all the input signals do not arrive necessarily at the same time in an actual circuit; there is always a specific signal, which is often delayed from others. The delay time of the entire logic circuit in such a case becomes the sum of the delay time of the circuit itself and the delay time of the input signal, which is delayed from others. In other words, even when the delay time of an object path is small, if there is any signal which arrives extremely late in the path, then the operation speed of the entire circuit is decided by the operation speed of the path. Consequently, if there is any input signal that is delayed extremely, the logic circuit should be formed so that the number of steps in the path related to the input signal is reduced by all means and the delay times of all the paths in the circuit become equal.
SUMMAERY OF THE INVENTION
Under such the circumstances, it is an object of the present invention to provide a fast logic circuit by arranging the number of steps so as to be equal in all the paths of the logical circuit and avoiding existence of a critical path whose delay time is extremely large.
It is another object of the present invention to provide a fast logic circuit formed so that if a specific input signal is far delayed from others, the delay time is taken into account thereby to arrange the number of steps is reduced by all means in the path related to the delayed signal when in forming the object logical circuit.
It is further another object of the present invention to provide a method for forming a logic circuit that can avoid having a critical path whose delay time is extremely large.
It is further another object of the present invention to provide a method for forming a logic circuit that can avoid having a critical path whose delay time is extremely large by considering an increase of the delay time of a specific input signal, which is expected to be delayed extremely from others.
In order to achieve the above objects, a preferred form of the present invention is a logic circuit (C
1
shown in
FIG. 1
) including: the first selector (S
1
) in which the control input S is controlled by the first input signal (IN
1
), and the input signal I
1
or I
0
is controlled by the second input signal (IN
2
), and the output O is connected to the first node (N
1
); and the third selector (S
3
) in which the control input S is controlled by the first node (N
1
), the input I
1
is controlled by the third input signal (IN
3
), the input I
0
is controlled by the first input signal (IN
1
), and the output O is connected to the first output signal (OUT
1
).
Another preferred form of the present invention is a

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