Logic circuit and its forming method

Details Logic circuit and its forming method Logic circuit and its forming method

1998-11-23

2000-09-26

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326113, 326106, 326108, 326 83, 326112, 327407, 327408, H03K 19094

Patent

active

061247367

ABSTRACT:
This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

REFERENCES:
patent: 5040139 (1991-08-01), Tran
patent: 5162666 (1992-11-01), Tran
patent: 5200907 (1993-04-01), Tran
patent: 5440245 (1995-08-01), Galbraith et al.
patent: 5625303 (1997-04-01), Jamshidi
patent: 5977792 (1999-11-01), Mehendale
IEEE 1994 Custom Integrated Circuits Conference, pp. 603-606.
IEEE Journal of Solid-State Circuits, vol. 25, No. 2, pp. 388-395.
IEEE 1993 International Solid-State Circuits Conference, Digest of Technical Papers, pp. 90-91.

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