Logic circuit, address decoder circuit and semiconductor memory

Details Logic circuit, address decoder circuit and semiconductor memory Logic circuit, address decoder circuit and semiconductor memory

2011-07-19

2011-07-19

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C365S230060, C365S230010, C326S104000

Reexamination Certificate

active

07982505

ABSTRACT:
Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.

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