Logic circuit

Details Logic circuit Logic circuit

2001-06-26

2002-12-10

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

C326S115000, C326S127000

Reexamination Certificate

active

06492842

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a logic circuit such as an OR/NOR circuit, an XOR/XNOR circuit, a selector circuit or a latch circuit, and more particularly to a logic circuit which can operate at a high speed with a low power supply voltage.
A demand to lower the operating voltage of a logic circuit is increasing from the point of view of refinement of a process or reduction of power consumption. Thus, a configuration of a conventional differential circuit which is a basic logic circuit is described first, and then restriction conditions to lower the operating voltage are described.
An example of circuit configuration of a differential circuit wherein a bipolar element is used is shown in FIG.
13
. Referring to
FIG. 13
, the differential circuit shown includes differential pair transistors Q
201
and Q
202
whose emitters are connected commonly, a current source I
201
connected between the emitter common connecting point of the differential pair transistors Q
201
and Q
202
and the ground, and a pair of resistors R
201
and R
202
connected between the collectors of the differential pair transistors Q
201
and Q
202
and a power supply line (power supply voltage VCC), respectively.
A circuit of a form which includes the differential circuit or a modification to the differential circuit is generally referred to as ECL (Emitter Coupled Logic) circuit. It is to be noted that the following argument applies substantially similarly to a circuit which employs a MOS element. In the differential circuit shown in
FIG. 13
, a differential signal AP/AN inputted to the input terminals of the differential circuit determines a differential signal ZP/ZN from output terminals of the differential circuit. Although the logic operation of the differential circuit normally is that of a buffer circuit, actually the differential circuit otherwise operates also as a NOT circuit depending upon the correspondence between the signal levels and the logic values.
For example, if the relationship AP>AN between the potentials AP and AN at the input terminals corresponds to the “true” of the logic value and the relationship ZP>ZN between the potentials ZP and ZN at the output terminals corresponds to the “true” of the logic value, then the circuit of
FIG. 13
operates as a mere buffer circuit. On the other hand, if the logic correspondence of the input or the output is reversed, for example, if ZP>ZN corresponds to the “false” of the logic value, then the same circuit now operates as a NOT circuit.
It is to be noted that this is a common technique used in configuration of a logic circuit which uses a differential signal. In other words, the logic reversal (NOT) can be implemented only by connecting a differential signal reversely.
Since a differential circuit by itself in most cases has an insufficient driving capacity for a load, an emitter follower is often added to an output stage of the differential circuit. In particular, referring to
FIG. 14
, the differential circuit shown in
FIG. 13
additionally includes a series circuit of a transistor Q
203
and a current source I
202
and another series circuit of a transistor Q
204
and a current source I
203
connected in parallel to each other between the power supply line and the ground. The bases of the transistors Q
203
and Q
204
are connected to the collectors of the differential pair transistors Q
201
and Q
202
, respectively, and a differential output is derived from the emitters of the transistors Q
203
and Q
204
.
Where the configuration wherein the emitter follower transistors Q
203
and Q
204
are added to the output stage of the differential circuit in this manner is adopted, the output logic level drops by the base-emitter voltage VBE of the emitter follower transistors Q
203
and Q
204
. Since a conventional ECL circuit uses a comparatively high voltage around 4.5 V as such power supply voltage VCC, the drop of such a voltage as mentioned above does not matter very much.
One of advantages of an ECL circuit is that, since it uses a technique of series gating or wired ORing of emitter followers, various logic functions can be realized without so much increasing the delay of a signal. In the following, several examples of such circuit are described.
The first example is a series gate AND circuit, and a circuit configuration of it is shown in FIG.
15
. It is to be noted that, in
FIG. 15
, like elements to those of
FIG. 13
are denoted by like reference characters. Referring to
FIG. 15
, the series gate AND circuit includes differential pair transistors Q
205
and Q
206
provided on the ground side with respect to the differential pair transistors Q
201
and Q
202
and having the emitters connected commonly.
The collector of the transistor Q
205
is connected to the emitter common connecting point of the differential pair transistors Q
201
and Q
202
, and the collector of the transistor Q
206
is connected to the ZP side output terminal together with the collector of the transistor
0202
. Further, the current source I
201
is connected between the emitter common connecting point of the differential pair transistors Q
205
and Q
206
and the ground.
In the AND circuit having the configuration described above, where the potentials at the input terminals of the A system are represented by AP and AN and the potentials at the input terminals of the B system by BP and BN while the potentials at the output terminals by ZP and ZN, ZP >ZN is satisfied only when AP >AN and BP >BN.
This condition can be written by a logic formula as
Z=A
B  (1)
In the expression (1), the “true” of the logic variable “A” is allocated to the state of AP >AN. This similarly applies to “B” and “Z”. The mark “
” represents the logic AND.
Here, in order to prevent the transistor Q
205
from being saturated, it is required that the signal level of the B system side be lower than that of the A system side. Although multi-stage series gating is possible with an ECL circuit, as the number of stages increases, a correspondingly lower logic level is required. Consequently, the number of stages of possible series gating is restricted.
Where the De Morgan theorem is used, the negation of the both sides of the expression (1) is given by
!
Z
=(
A
B
)=!
A
!B
  (2)
where “!” represents the reversal of the logic, and “
” represents the logic OR. The expression (2) indicates that, if the correspondence of the inputs/outputs to the logic values is reversed, then the same circuit functions as a logic OR circuit.
As another method for realizing the logic OR, a wired OR connection or a collector dot is known. An example of OR circuit which employs a wired OR connection and a collector dot is shown in FIG.
16
. Referring to
FIG. 16
, like elements to those of
FIG. 14
are denoted by like reference characters, and the circuit shown in
FIG. 16
adopts a quite same configuration of a differential circuit as that of
FIG. 14
in which it has an emitter follower configuration at an output stage thereof.
Meanwhile, the emitter common connecting point of the differential pair transistors Q
205
and Q
206
is connected to the ground through a current source I
204
. The collector of the transistor Q
205
is connected to the collector of the transistor Q
201
. The connecting point between the two collectors is a collector dot. Meanwhile, the collector of the transistor Q
206
is connected to the power supply line through a resistor R
203
.
The base of a transistor Q
207
is connected to the collector of the transistor Q
206
. The collector of the transistor Q
207
is connected to the power supply line, and the emitter of the transistor Q
207
is connected commonly to the emitter of the transistor Q
204
. The connection of the emitters is a wired OR connection and connected to the ground through the current source I
203
.
In the circuit configuration described above, the potential ZP at the output terminal connected to the wired OR connection depends upon a higher one of base voltages at

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