Logic circuit

Details Logic circuit Logic circuit

2000-05-30

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S093000, C326S112000

Reexamination Certificate

active

06320421

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic circuit, or more particularly, to a logic circuit acting as a flip-flop circuit with a data-selecting function.
2. Description of the Related Art
For constructing a logic circuit that acts at a high speed, it is generally known to adopt a pipeline structure. The pipeline structure is such that: flip-flops are included in an combinational circuit; the combinational circuit is divided into a plurality of stages segmented with the flip-flops; and the stages are worked simultaneously in order to carry out processing. Adoption of the pipeline structure improves a throughput and speeds up the action of the whole logic circuit. Thus, the flip-flops serve as basic circuits required for realizing a logic circuit.
FIG. 2
shows an example of a flip-flop circuit employed conventionally. The flip-flop circuit consists of five inverters IV
1
to IV
5
, two tristate inverters TIV
1
and TIV
2
, and two transmission gates TG
1
and TG
2
. The flip-flop circuit inputs a voltage of an input signal I
1
developed with the rising of a clock signal CLK that is a reference signal based on which the circuit acts. The flip-flop circuit then outputs the signal through an output port O
1
and retains the state thereof until the next rising of the clock signal CLK.
FIG. 3
is a truth table indicating the action of the flip-flop circuit shown in FIG.
2
.
When the flip-flop circuit shown in
FIG. 2
is actually produced, it causes a propagation delay as indicated in the timing chart of FIG.
4
. Therefore, a signal is developed at the output port O
1
in a certain time (delay time td) after the rising of the clock signal CLK. Moreover, circuit elements causing a propagation delay are interposed between the input port I
1
and a node n
1
at which data is stored. For this reason, a signal to be applied to the input port I
1
must be produced by a time, which is longer than the certain time (setup time ts), earlier than the rising of the clock signal CLK.
FIG. 5
shows an example of a pipeline circuit having a combinational circuit Comb interposed between flip-flop circuits F/F. In the pipeline circuit, a cycle time tcyc is determined with the sum of a delay time caused by the flip-flop circuits themselves (a delay time td plus a setup time ts) and a delay time occurring between the flip-flop circuits (that is, a delay time tcomb caused by the combinational circuit). Whether the delay times can be reduced as much as possible has a significant meaning in designing a pipeline circuit that acts at a high speed. The cycle time tcyc required by the pipeline circuit is expressed as follows:
tcyc=ts+td+tcomb  (1)
For allowing a logic circuit to act at a high speed, the cycle time tcyc must be reduced. However, the combinational circuit Comb cannot be excluded in order to realize a large-scale integration (LSI) having an intended logic function. Moreover, a delay time caused by one circuit element is shorter than that caused by a flip-flop circuit F/F. Therefore, realizing a flip-clop circuit that acts at a high speed is essential to an increase in the speed at which a logic circuit acts.
Circuitry having a flip-flop circuit that includes a circuit element for realizing an added function is known as a means for speeding up the action of a logic circuit using a flip-flop circuit. The circuit has been disclosed in, for example, Japanese Unexamined Patent Publication Nos. 7-231246 and 6-45879.
The Japanese Unexamined Patent Publication No. 7-231246 describes circuitry having a latch circuit, which is a component of a flip-flop circuit, with a NAND function. When the latch circuit having the NAND function is used to construct a flip-flop circuit, an NAND element is substituted for the inverter IV
3
or IV
5
in the flip-flop circuit shown in FIG.
2
. The substitution realizes a flip-flop circuit having the NAND function.
Moreover, the Japanese Unexamined Patent Publication No. 6-45879 describes circuitry having a flip-flop circuit with a data-selecting function. The circuitry is concerned with a flip-flop circuit having a master/slave structure. The flip-flop circuit with a data-selecting function is realized by adding to a master stage a feature for latching a plurality of data items and a feature for selecting one data from the data items and transferring the selected data to a slave stage.
However, in the flip-flop circuit with a data-selecting function disclosed in the Japanese Unexamined Patent Publication No. 6-45879, three circuits must be included for holding data. This leads to a large area. Besides, the number of selectable data items is two.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a logic circuit acting as a flip-flop circuit with a data-selecting function that acts at the same speed as a conventional flip-flop circuit despite its data selecting function for selecting two data items. Nevertheless, the logic circuit with a data-selecting function occupies a smaller area than a conventional flip-flop circuit with a data-selecting function.
Another object of the present invention is to provide a logic circuit acting as a flip-flop circuit with a data-selecting function capable of selecting three or more data items.
A first logic circuit in accordance with the present invention has first and second data input ports, first and second select signal input ports, a reference signal input port, and an output port. Either of first and second data items input through the first and second data input terminals is selected based on select signals of opposite polarities input through the first and second select signal input ports. Data selected based on the select signals synchronously with a reference signal input through the reference signal input port is output through the output port. The first logic circuit thus acts as a two-input flip-flop circuit with a data-selecting function.
The first logic circuit has components described below. Hereinafter, components identical to those shown in
FIG. 6
will be assigned the same reference numerals. The first logic circuit consists of a first inverter IV
10
, a second inverter IV
11
, a first NOR circuit
12
a
, a second NOR circuit
12
b
, a first transmission gate TG
10
a
, a second transmission gate TG
10
b
, and third transmission gate TG
11
. The first inverter IV
10
has an output terminal thereof connected to a first transmission gate through (for example, a transmission gate TG
11
in the circuitry shown in FIG.
6
). The second inverter IV
11
has an output terminal thereof connected to the output port O
1
. The first NOR circuit
12
a
has the first select signal input port /sel connected to one input terminal thereof, and has the reference signal CLK applied to the other input terminal thereof. The second NOR circuit
12
b
has the second select signal input port sel connected to one input terminal thereof and has the reference signal applied to the other input terminal thereof. The first transmission gate TG
10
a
is connected between the first NOR circuit and the input terminal of the first inverter, and controlled based on an output of the first NOR circuit. The second transmission gate TG
10
b
is connected between the second data input terminal
12
and the input terminal of the first inverter, and controlled based on an output of the second NOR circuit. The third transmission gate TG
11
is connected between the first and second inverters and controlled based on the reference signal input through the reference signal input port.
In the foregoing first logic circuit, the first, second, and third transmission gates may be, like those shown in
FIG. 14
, realized with n-channel field-effect transistors and p-channel field-effect transistors. In this case, signals used to control the first and second transmission gates include the output signals of the first and second NOR circuits and the reverse signals of the output signals. Signals used to control the third transmission gate include the re

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