Logic circuit

Details Logic circuit Logic circuit

1999-11-24

2001-11-27

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S106000, C326S108000, C326S119000

Reexamination Certificate

active

06323691

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to logic circuits that may be used in a semiconductor memory, and more particularly to logic circuits that may be used in semiconductor memory decoder circuits.
BACKGROUND OF THE INVENTION
Semiconductor memories can include a number of storage locations that can be accessed by the application of an address value. Address values can be received in binary form and subsequently decoded by decoder circuits to access one or more storage locations. In such arrangements, a decoder circuit can have a considerable impact on the access time of a semiconductor memory. Faster semiconductor memories can lead to faster and more powerful electronic systems.
FIG. 9
sets forth a schematic diagram of a conventional decoder circuit. The conventional decoder circuit is a logic circuit designated by the general reference character
900
. The logic circuit
900
can include p-channel and n-channel field-effect transistors (FETs) which will be referred to herein as a particular type of FET, the metal-oxide-semiconductor FET (MOSFET). Accordingly, p-channel FETs will be referred to as PMOS transistors and n-channel FETs will be referred to as NMOS transistors.
Logic circuit
900
includes PMOS transistors
902
and
904
that can serve as load devices and NMOS transistors
906
,
908
and
910
that perform logic functions. An inverter
912
can invert a logic value. An output terminal is shown as item
914
and input terminals are shown as items
916
,
918
and
920
.
PMOS transistors
902
and
904
can be connected to one another in parallel. The sources of PMOS transistors (
902
and
904
) can be connected to a positive power supply VCC. NMOS transistors
906
,
908
and
910
can be connected in series to one another, and to PMOS transistors
902
and
904
. The source of NMOS transistor
910
can be connected to a reference power supply (e.g., “ground”). The general arrangement of transistors (
902
to
910
) can be conceptualized as a three input NAND gate.
Logic circuit
900
can include an internal terminal formed by the drain-drain connection of PMOS transistors
902
/
904
and NMOS transistor
906
. The internal terminal can be connected to the input terminal of inverter
912
. The output terminal of inverter
912
can be connected to the gate of transistor
904
and output terminal
914
.
Input terminal
916
can be a clock input terminal that receives a clock signal CLK and is connected to the gate of PMOS transistor
902
and the gate of NMOS transistor
906
. Input terminal
918
can be a first signal input terminal that receives a signal D
0
and is connected to the gate of NMOS transistor
908
. Input terminal
920
can be a second signal input terminal that receives a signal D
4
and is connected to the gate of NMOS transistor
910
.
The operation of the conventional logic circuit
900
will now be described. Initially, the CLK signal supplied to clock input terminal
916
can be at a low logic level. PMOS transistor
902
can be in an active state and provide a relatively low load impedance. The input terminal of inverter
912
can be pulled to a logic high value. The high value can be inverted by inverter
912
resulting in output terminal
914
being driven low.
When the output of inverter
912
is low, PMOS transistor
904
can be in an active state and provide a relatively low load impedance. In this arrangement, even if clock signal CLK transitions high, turning off transistor
902
, the internal terminal can remain high. The high internal terminal can be inverted by inverter
912
, keeping PMOS transistor
904
in the active state. Thus, the output terminal
914
can remain low (assuming that an NMOS transistor
908
or
910
remains turned off).
In the event the CLK signal is at a high level at the same time the D
0
and D
4
signals are at a high level, NMOS transistors
906
,
908
and
910
can be activated. The D
0
and D
4
signals could be generated by predecoder circuits (not shown) that can “predecode” applied address values. If NMOS transistors
906
,
908
and
910
are activated, the three transistors can “sink” more current than PMOS transistor
904
can “source” and the potential of the internal node (the input terminal of inverter
912
) can be pulled low. This value is inverted by inverter
912
resulting in output terminal
914
being driven high. A logic high at output terminal
914
can turn off PMOS transistor
904
. With PMOS transistor
904
turned off, essentially no current will flow through the source-drain paths of PMOS transistor
904
and NMOS transistors
906
,
908
and
910
. The resulting logic high at output terminal
914
can be an active decode output X
0
.
Thus, in the conventional logic circuit
900
, a decode output X
0
in response to input signals D
0
and D
4
can be generated when the CLK signal transitions to a logic high level.
As noted above, in a conventional logic circuit approach such as that set forth in
FIG. 9
, the series arrangement of NMOS transistors
906
,
908
and
910
must sink enough current to lower the potential at the input terminal of inverter
912
. The potential must be lowered enough to cause the output of inverter
912
to be high enough to begin to turn off PMOS transistor
904
. Thus, unless the current sinking capacity of NMOS transistors
906
,
908
and
910
is substantially larger than the current sourcing capacity of PMOS transistor
904
, it may take a considerable amount of time to lower the potential at the input terminal of inverter
912
. This can increase the time between transitions in the CLK signal and input signals D
0
and D
4
and a resulting active decode output X
0
. Consequently, the operating speed of a conventional logic circuit can be limited.
Another drawback to conventional logic circuit approaches can be the current consumed by the logic circuit. In the particular case of
FIG. 9
, current can flow through PMOS transistor
904
and NMOS transistors
906
,
908
and
910
until the output of inverter
912
turns off transistor
904
.
One skilled in the art would recognize that current consumption and peak current requirements can be important aspects of an integrated circuit.
In the arrangement of
FIG. 9
, the operating speed of the logic circuit
900
may be increased by decreasing the current sourcing capacity of PMOS transistor
904
without any corresponding decrease in the current sinking capacity of NMOS transistors
906
,
908
and
910
. While such an arrangement may increase the speed at which the input terminal of inverter
912
transitions from high to low, such an arrangement may also decrease the speed at which the input terminal of inverter
912
transitions from low to high.
SUMMARY OF THE INVENTION
It is an object of present invention to provide a logic circuit that can have a higher speed and lower current consumption than conventional circuits, such as that described above. Such a logic circuit can change the impedance of a load field effect transistor synchronously with an input signal.
A logic circuit according to one embodiment of the present invention can include at least one logical operation transistor that can perform a logic operation in response to a number of input signals and a load transistor that can serve as a load for the logical operation transistor. A load impedance control circuit can be provided that changes the impedance of the load transistor by controlling the potential of a load transistor control terminal.
Because a load impedance control circuit according to the present invention can be provided that changes the impedance of a load transistor, the impedance of the load transistor can be changed in synchronism with an expected change in an output signal of the logic circuit. Two particular examples are described below.
As a first example, a logic circuit may include a load transistor and a logical operation transistor. The logic circuit can provide a logic low output value by activating the logical operation transistor and sinking current sourced by the load transistor. The speed

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