Logic cell which can be configured as a latch without static one

Details Logic cell which can be configured as a latch without static one Logic cell which can be configured as a latch without static one

1995-10-26

1997-07-08

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

326 37, 327198, 327199, H03K 3289

Patent

active

056465475

ABSTRACT:
A latch may be formed as a two-part structure, one part for data input and one part for feeding back the data to form the latch. A clock signal controls whether data from a data input terminal will be forwarded to the output or whether the output signal will be provided as input and forwarded, thus forming the latch. A problem called the static ones hazard, namely registering a logical 0 when data input is logical 1, can occur with a latch of this logic structure when the circuit is entering the latch mode. In accordance with the invention, this static ones hazard is avoided by controlling trip points in the gates of the cell and input buffers of the cell so that the cell implements a make-before-break transition.

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D. E. Smith et al, "Regain Lost I/O Ports with Erasable PLD's", Electronic Design, vol. 35, No. 7, Mar. 19, 1987, pp. 151-154.
Birkner, J.; Chang, A.; Chua, H.T.; Chao, A.; Gordon, K; Kleinman, B.; Kolze, P. and Wong, R.; "A Very High-Speed Field Programmable Gate Array Using Metal-to-Metal Antifuse Programmable Elements", QuickLogic Corporation, paper 1.7, Session 1, pp. 1-6, IEEE 1991 Custom Integrated Circuits Conf., May 12, 1991.

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