Logic block used as dynamically configurable logic function

Details Logic block used as dynamically configurable logic function Logic block used as dynamically configurable logic function

2001-02-16

2002-05-07

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S040000, C326S041000

Reexamination Certificate

active

06384627

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to programmable logic devices, more particularly to using programmable logic devices to implement a selected logic function.
BACKGROUND OF THE INVENTION
As programmable logic devices (PLDs), and particularly field programmable gate arrays (FPGAs) have become more powerful, it has become both possible and practical to use them to perform more powerful functions more efficiently.
An early improvement to the basic FPGA structure allowed a lookup table (function generator) to either be loaded as part of a configuration bitstream or be loaded from the interconnect structure. This option was particularly useful for forming small distributed RAM in the memory cells of the lookup tables. The option also allowed for changing configuration of a lookup table without reloading a bitstream into the entire FPGA. Freeman et al. in U.S. Pat. No. 5,343,406 entitled “Distributed Memory Architecture for a Configurable Logic Array and Method for Using Distributed Memory” discuss this possibility in their summary of the invention.
A recent introduction to the FPGA market from Xilinx,Inc., assignee of the present invention, is the Virtex® FPGA product line. (“Virtex” is a trademark of Xilinx,Inc. registered in the U.S. Xilinx, Inc is the assignee of the present patent application.) Like other FPGA devices, the Virtex product line uses configurable logic blocks with lookup tables for programming combinatorial logic functions. The Virtex product line uses enhanced function generators to provide three kinds of functions: lookup table for logic function, RAM for distributed memory storage, and shift register useful for FIFO and other operations common in communications applications. U.S. Pat. No. 6,118,298 by Bauer et al. entitled “STRUCTURE FOR OPTIONALLY CASCADING SHIFT REGISTERS” describes in detail the structure in which a function generator can be used as a lookup table, RAM, or shift register, and also describes a recent improvement in which shift registers can be cascaded to form longer shift registers.
FIG. 1
(taken from FIG. 8 of the above Bauer et al patent) shows a structure usable as both a lookup table and a 16-bit shift register. Signal “Shift” causes controller
800
to select between lookup table mode and shift register mode. In lookup table mode, multiplexer
200
receives and decodes four input signals I
0
through I
3
and decodes them to select the value in one of the 16 memory cells M
0
through M
15
to provide as output signal O. In shift register mode, data on line CFG_DIN are shifted from memory cell M
0
through consecutive memory cells to memory cell M
15
as controlled by clock signals Phi
1
and Phi
2
in clock controller
800
. Clock controller
800
generates non-overlapping clock signals to master and slave portions of the memory cells in response to clock signal CFG_CLK when enabled by enable signal CFG_EN.
FIG. 2
shows a symbol for a configurable shift register lookup table SRL16E that can be implemented as shown in FIG.
1
.
FIG. 3
illustrates another feature available in the Virtex FPGA from Xilinx, Inc. Function generator
903
provides output signal O. This signal O can serve as an output signal or can control carry multiplexer
923
. Also provided is two-input AND gate
61
that provides an input signal to carry multiplexer
923
. Use of this AND gate for multiplication is discussed in more detail by Chapman et al. in U.S. patent application Ser. No. 08/786,818 entitled “Configurable Logic Block with AND Gate for Efficient Multiplication in FPGAs”, incorporated herein by reference.
It is possible to use AND gate
61
to implement additional valuable functions.
SUMMARY OF THE INVENTION
According to the invention, a portion of an FPGA is configured to form a comparator. The features of the comparator are determined by values stored in lookup tables of the FPGA, and these lookup tables can be reconfigured without disturbing the remainder of the FPGA. In one embodiment, the comparator provides a trigger signal to a logic analyzer also formed in the FPGA, and causes the logic analyzer to start collecting data on logic functions implemented in yet another part of the FPGA. Comparators that perform both exact matching (A=B or A≠B) and relative matching (A>B, A<B, A≧B or A≦B) and one comparison that combines relative and exact matching are disclosed.
Preferably an FPGA having lookup tables that can be loaded as shift registers is used, and preferably the lookup tables can be cascaded to form longer shift registers, so that reconfiguration data can be shifted into a cascaded chain of lookup tables without having to address specific memory cells in the lookup tables and without having to connect lookup tables together through interconnect wiring of the FPGA.
Examples of exact matching of two variables, exact matching of a variable to a constant, relative matching (greater than or equal to) of a variable to a constant, and combined exact and relative matching are disclosed and discussed. Use of comparator for triggering a logic analyzer is also discussed.


REFERENCES:
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5818255 (1998-10-01), New et al.
patent: 5889413 (1999-03-01), Bauer et al.
patent: 5914616 (1999-06-01), Young et al.
patent: 6118298 (2000-09-01), Bauer et al.
patent: 6262597 (2001-07-01), Bauer et al.
U.S. Application No. 08/786,818, Chapman et al., filed Jan. 21, 1997.
U.S. Application No. 09/574,534, Bauer et al., filed May 19, 2000.

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